commit a37a0fefaaf61532c0b7ee5651234d4dc48bec81
author Steve Kelly <kd2cca@gmail.com> Sat Dec 19 00:03:11 2020 -0500
committer tonokip <tonokip@gmail.com> Sat Dec 19 01:33:55 2020 -0600
tree deb8e8be56cf5730789ff33b42ee4fa031500b93
parent 34fa3d15b40854a13e662b1c66344a40f0c73599

use external reset pin

verilog/rtl/rapcores.v

diff --git a/verilog/rtl/rapcores.v b/verilog/rtl/rapcores.v
index b1d46d6..f917124 100644
--- a/verilog/rtl/rapcores.v
+++ b/verilog/rtl/rapcores.v
@@ -124,6 +124,8 @@
     assign io_oeb[33] = 1'b1;    // DIRINPUT
     assign io_oeb[11] = 1'b1;    // ENINPUT
     assign io_oeb[10] = 1'b0;    // ENOUTPUT
+    assign io_oeb[9] = 1'b1;    //RESETIN
+
     // unused
     assign io_oeb[0] = 1'b0;    // JTAG I/O
     assign io_oeb[1] = 1'b0;    // SDO
@@ -134,7 +136,6 @@
     assign io_oeb[6] = 1'b0;    // Tx
     assign io_oeb[7] = 1'b0;    // IRQ
     assign io_oeb[8] = 1'b1;
-    assign io_oeb[9] = 1'b1;
 
 
     wire resetn;
@@ -152,7 +153,7 @@
 
         // IO Pads
         .CLK(wb_clk_i),
-        .resetn_in(resetn),
+        .resetn_in(io_in[9]),
         .CHARGEPUMP(io_out[15]),
         .analog_cmp1(io_in[25]),
         .analog_out1(io_out[27]),