Split the main power supply into managment and two user areas. Mostly
put back together again from phase2, although only the gpio testbench
has been updated, and the gpio tesbench is currently not passing although
most signals seem to be right. Modified the memory map to allow for an
additional word in the management I/O GPIO read/write data, and rewrote
the code to handle any number of I/Os in the user space, expanding the
memory map by one word for every 32 user GPIO pads (there are currently
37 user GPIO pads specified, so this change resolves issues with the
upper 5 pads; the last phase2 design defined only 32 user I/O pads).
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index af198c4..742977c 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -20,9 +20,21 @@
*/
module user_proj_example #(
- parameter IO_PADS = 32,
+ parameter IO_PADS = 37,
+ parameter PWR_PADS = 4,
parameter BITS = 32
)(
+`ifdef LVS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
