basic automated functional test
diff --git a/verilog/dv/caravel/rapcore/io_ports/io_ports_tb.v b/verilog/dv/caravel/rapcore/io_ports/io_ports_tb.v
index 3d9caee..410e501 100644
--- a/verilog/dv/caravel/rapcore/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/rapcore/io_ports/io_ports_tb.v
@@ -40,11 +40,8 @@
reg power1, power2;
reg power3, power4;
- wire gpio;
- wire [37:0] mprj_io;
- wire [16:0] mprj_io_0;
-
- assign mprj_io_0 = mprj_io[30:14];
+ wire gpio;
+ wire [37:0] mprj_io;
assign mprj_io[3] = 1'b1;
// External clock is used by default. Make this artificially fast for the
@@ -73,15 +70,70 @@
end
initial begin
- // Observe Output pins [7:0]
- wait(mprj_io_0 == 17'b01000011001100110);
- wait(mprj_io_0 == 17'b01100011000101110);
- wait(mprj_io_0 == 17'b01000011001100110);
- wait(mprj_io_0 == 17'b01100011001100011);
- wait(mprj_io_0 == 17'b01000011001100110);
- wait(mprj_io_0 == 17'b01110011000101110);
- wait(mprj_io_0 == 17'b01101011001100011);
- wait(mprj_io_0 == 17'b01100011001100011);
+ // Observe Output pins
+ wait(mprj_io[24] == 1'b1); // Move done =0
+ wait(mprj_io[37:36] == 2'b10); // DTR:CIPO
+ #1 $display("SPI response");
+ wait(mprj_io[37:36] == 2'b11);
+ wait(mprj_io[37:36] == 2'b10);
+ #1 $display("Encoder data transmit");
+ wait(mprj_io[15] == 1'b1);
+ wait(mprj_io[15] == 1'b0);
+ wait(mprj_io[15] == 1'b1);
+ #1 $display("Charge pump switching");
+ wait(mprj_io[27] == 1'b1);
+ wait(mprj_io[27] == 1'b0);
+ wait(mprj_io[27] == 1'b1);
+ wait(mprj_io[28] == 1'b1);
+ wait(mprj_io[28] == 1'b0);
+ wait(mprj_io[28] == 1'b1);
+ #1 $display("Both ADC outputs switching");
+ wait(mprj_io[24] == 1'b1);
+ #1 $display("DDA running");
+ wait(mprj_io[30] == 0); // Step out
+ wait(mprj_io[31] == 0); // Direction output only tested in one direction
+ wait(mprj_io[30] == 1); // Step out
+ wait(mprj_io[30] == 0); // Step out
+ #1 $display("Step out switching");
+ wait(mprj_io[23] == 1'b1);
+ wait(mprj_io[19] == 1'b1);
+ wait(mprj_io[16] == 1'b1);
+ wait(mprj_io[20] == 1'b1);
+ wait(mprj_io[21] == 1'b1);
+ wait(mprj_io[18] == 1'b1);
+ wait(mprj_io[14] == 1'b1);
+ wait(mprj_io[17] == 1'b1);
+
+ wait(mprj_io[23] == 1'b0);
+ wait(mprj_io[19] == 1'b0);
+ wait(mprj_io[16] == 1'b0);
+ wait(mprj_io[20] == 1'b0);
+ wait(mprj_io[21] == 1'b0);
+ wait(mprj_io[18] == 1'b0);
+ wait(mprj_io[14] == 1'b0);
+ wait(mprj_io[17] == 1'b0);
+
+ wait(mprj_io[23] == 1'b1);
+ wait(mprj_io[19] == 1'b1);
+ wait(mprj_io[16] == 1'b1);
+ wait(mprj_io[20] == 1'b1);
+ wait(mprj_io[21] == 1'b1);
+ wait(mprj_io[18] == 1'b1);
+ wait(mprj_io[14] == 1'b1);
+ wait(mprj_io[17] == 1'b1);
+
+ wait(mprj_io[23] == 1'b0);
+ wait(mprj_io[19] == 1'b0);
+ wait(mprj_io[16] == 1'b0);
+ wait(mprj_io[20] == 1'b0);
+ wait(mprj_io[21] == 1'b0);
+ wait(mprj_io[18] == 1'b0);
+ wait(mprj_io[14] == 1'b0);
+ wait(mprj_io[17] == 1'b0);
+ #1 $display("Bridge outputs switching");
+ //wait(mprj_io[10] == // Enable output
+ //wait(mprj_io[24] == // Move done
+ //wait(mprj_io[29] == // Halt
$display("Monitor: Test 1 RAPcores Passed");
$finish;
end
@@ -107,8 +159,8 @@
//bootdone <= 1'b1;
end
- always @(mprj_io) begin
- #1 $display("MPRJ-IO state = %b ", mprj_io[37:0]);
+ always @(mprj_io[5]) begin
+ #1 $display("Booting ", mprj_io[37:5]);
end
wire flash_csb;
