initial integration
diff --git a/caravel.sh b/caravel.sh index 7d65985..e79d5b0 100755 --- a/caravel.sh +++ b/caravel.sh
@@ -1,9 +1,8 @@ #! /usr/bin/env bash export PDK_ROOT=`pwd`/pdk_root -export OPENLANE_ROOT=`pwd`/openlane +export OPENLANE_ROOT=`pwd`/openlane_repo echo $PDK_ROOT echo $OPENLANE_ROOT -git clone ../caravel -cd caravel/openlane -make user_project_wrapper OPENLANE_IMAGE_NAME=openlane:rc5 +cd openlane +make user_proj_example OPENLANE_IMAGE_NAME=openlane:rc5
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl index ca6d3e9..15344f4 100644 --- a/openlane/user_proj_example/config.tcl +++ b/openlane/user_proj_example/config.tcl
@@ -3,15 +3,28 @@ set ::env(DESIGN_NAME) user_proj_example set ::env(VERILOG_FILES) "\ - $script_dir/../../verilog/rtl/defines.v \ - $script_dir/../../verilog/rtl/user_proj_example.v" + $script_dir/../../verilog/rtl/defines.v \ + $script_dir/../../rapcores/src/constants.v \ + $script_dir/../../rapcore_caravel_defines.v \ + $script_dir/../../rapcores/src/macro_params.v \ + $script_dir/../../rapcores/src/top.v \ + $script_dir/../../verilog/rtl/user_proj_example.v \ + $script_dir/../../rapcores/src/stepper.v \ + $script_dir/../../rapcores/src/spi.v \ + $script_dir/../../rapcores/src/quad_enc.v \ + $script_dir/../../rapcores/src/pwm.v \ + $script_dir/../../rapcores/src/microstepper/microstepper_top.v \ + $script_dir/../../rapcores/src/microstepper/microstep_counter.v \ + $script_dir/../../rapcores/src/microstepper/cosine.v \ + $script_dir/../../rapcores/src/microstepper/analog_out.v \ + $script_dir/../../rapcores/src/microstepper/chargepump.v \ + $script_dir/../../rapcores/src/microstepper/mytimer.v" -set ::env(CLOCK_PORT) "" -set ::env(CLOCK_NET) "counter.clk" +set ::env(CLOCK_PORT) "wb_clk_i" set ::env(CLOCK_PERIOD) "10" set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 600 600" +set ::env(DIE_AREA) "0 0 2500 3500" set ::env(DESIGN_IS_CORE) 0 set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg @@ -19,4 +32,4 @@ # set ::env(FP_CONTEXT_LEF) $script_dir/../user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef set ::env(PL_BASIC_PLACEMENT) 1 -set ::env(PL_TARGET_DENSITY) 0.15 +set ::env(PL_TARGET_DENSITY) 0.01
diff --git a/rapcore_caravel_defines.v b/rapcore_caravel_defines.v new file mode 100644 index 0000000..c63166f --- /dev/null +++ b/rapcore_caravel_defines.v
@@ -0,0 +1,31 @@ + +// Enable SPI Interface +`define SPI_INTERFACE + +// Use PLL for higher SPI frequencies +//`define SPIPLL + +// Enable Buffer DTR pin +`define BUFFER_DTR + +// Enable Move Done Pin +`define MOVE_DONE + +// Enable Halt Input +`define HALT + +// Motor Definitions +//`define DUAL_HBRIDGE 1 +`define ULTIBRIDGE 1 + +// Encoder Count +`define QUAD_ENC 1 + +// External Step/DIR Input +`define STEPINPUT + +// Output Step/DIR signals +`define STEPOUTPUT + +// Change the Move Buffer Size. Should be power of two +//`define MOVE_BUFFER_SIZE 4
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v index 3445aa0..904bc71 100644 --- a/verilog/rtl/user_proj_example.v +++ b/verilog/rtl/user_proj_example.v
@@ -63,7 +63,7 @@ wire [`MPRJ_IO_PADS-1:0] io_out; wire [`MPRJ_IO_PADS-1:0] io_oeb; - wire [31:0] rdata; + wire [31:0] rdata; wire [31:0] wdata; wire [BITS-1:0] count; @@ -72,7 +72,7 @@ wire [31:0] la_write; // WB MI A - assign valid = wbs_cyc_i && wbs_stb_i; + assign valid = wbs_cyc_i && wbs_stb_i; assign wstrb = wbs_sel_i & {4{wbs_we_i}}; assign wbs_dat_o = rdata; assign wdata = wbs_dat_i; @@ -83,75 +83,41 @@ // LA assign la_data_out = {{(127-BITS){1'b0}}, count}; - // Assuming LA probes [63:32] are for controlling the count register + // Assuming LA probes [63:32] are for controlling the count register assign la_write = ~la_oen[63:32] & ~{BITS{valid}}; - // Assuming LA probes [65:64] are for controlling the count clk & reset + // Assuming LA probes [65:64] are for controlling the count clk & reset assign clk = (~la_oen[64]) ? la_data_in[64]: wb_clk_i; assign rst = (~la_oen[65]) ? la_data_in[65]: wb_rst_i; - counter #( - .BITS(BITS) - ) counter( - .clk(clk), - .reset(rst), - .ready(wbs_ack_o), - .valid(valid), - .rdata(rdata), - .wdata(wbs_dat_i), - .wstrb(wstrb), - .la_write(la_write), - .la_input(la_data_in[63:32]), - .count(count) + + top top ( + + // IO Pads + .CLK(clk), + .CHARGEPUMP(io_out[15]), + .analog_cmp1(io_in[25]), + .analog_out1(io_out[27]), + .analog_cmp2(io_in[26]), + .analog_out2(io_out[28]), + .PHASE_A1(io_out[23]), + .PHASE_A2(io_out[19]), + .PHASE_B1(io_out[16]), + .PHASE_B2(io_out[20]), + .PHASE_A1_H(io_out[21]), + .PHASE_A2_H(io_out[18]), + .PHASE_B1_H(io_out[14]), + .PHASE_B2_H(io_out[17]), + .ENC_B(io_in[18]), + .ENC_A(io_in[19]), + .BUFFER_DTR(io_out[12]), + .MOVE_DONE(io_out[24]), + .HALT(io_in[29]), + .SCK(io_in[10]), + .CS(io_in[9]), + .COPI(io_in[8]), + .CIPO(io_out[11]) ); endmodule -module counter #( - parameter BITS = 32 -)( - input clk, - input reset, - input valid, - input [3:0] wstrb, - input [BITS-1:0] wdata, - input [BITS-1:0] la_write, - input [BITS-1:0] la_input, - output ready, - output [BITS-1:0] rdata, - output [BITS-1:0] count -); - reg ready; - reg [BITS-1:0] count; - reg [BITS-1:0] rdata; - - always @(posedge clk) begin - if (reset) begin - count <= 0; - ready <= 0; - end else begin - ready <= 1'b0; - if (~|la_write) begin - count <= count + 1; - end - if (valid && !ready) begin - ready <= 1'b1; - rdata <= count; - if (wstrb[0]) count[7:0] <= wdata[7:0]; - if (wstrb[1]) count[15:8] <= wdata[15:8]; - if (wstrb[2]) count[23:16] <= wdata[23:16]; - if (wstrb[3]) count[31:24] <= wdata[31:24]; - end - end - end - - genvar i; - generate - for(i=0; i<BITS; i=i+1) begin - always @(posedge clk) begin - if (la_write[i]) count[i] <= la_input[i]; - end - end - endgenerate - -endmodule `default_nettype wire