commit 887ec0b711bef953809a2a3f24c800c532512f8c
author Steve Kelly <kd2cca@gmail.com> Thu Dec 17 21:31:53 2020 -0500
committer Steve Kelly <kd2cca@gmail.com> Thu Dec 17 21:31:53 2020 -0500
tree 1cbae3b49f384fc96bdc94ef5cf1ef2bf96d5e3a
parent 0e2a7a3691b8df065370694fc93282ebd0c06040

naming fixes

verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v

diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
index 222e5e3..26a80a4 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -42,7 +42,7 @@
 `ifdef PROJ_GL
   `include "gl/rapcore.v"
 `else
-  `include "rapcore_caravel.v"
+  `include "rapcores.v"
 `endif
 
 `include "caravel.v"
@@ -96,7 +96,7 @@
 	    wait(mprj_io_0 == 8'h07);
             wait(mprj_io_0 == 8'h08);
 	    wait(mprj_io_0 == 8'h09);
-            wait(mprj_io_0 == 8'h0A);   
+            wait(mprj_io_0 == 8'h0A);
 	    wait(mprj_io_0 == 8'hFF);
 	    wait(mprj_io_0 == 8'h00);
 
@@ -301,4 +301,3 @@
     );
 endmodule
 `default_nettype wire
-

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 9de1bc4..6e33af2 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -79,7 +79,7 @@
     /* User project is instantiated  here   */
     /*--------------------------------------*/
 
-    rapcore_caravel rapcore_caravel0 (
+    rapcores rapcores0 (
 
 `ifndef SIM
     `ifdef USE_POWER_PINS