rapcore upstream
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 6e33af2..1515543 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -104,10 +104,10 @@
 	.wbs_stb_i(wbs_stb_i),
 	.wbs_we_i(wbs_we_i),
 	.wbs_sel_i(wbs_sel_i),
-	.wbs_adr_i(wbs_adr_i),
-	.wbs_dat_i(wbs_dat_i),
+	//.wbs_adr_i(wbs_adr_i),
+	//.wbs_dat_i(wbs_dat_i),
 	.wbs_ack_o(wbs_ack_o),
-	.wbs_dat_o(wbs_dat_o),
+	//.wbs_dat_o(wbs_dat_o),
 
 	// Logic Analyzer