commit 61dce92ffadeb8742dadd290f03bc354f1405b8d
author Manar <manarabdelatty@aucegypt.edu> Tue Nov 10 19:26:28 2020 +0200
committer Manar <manarabdelatty@aucegypt.edu> Tue Nov 10 19:32:02 2020 +0200
tree 8751c6a1c0dea69e4e7b2823bd62d5dfc10a3847
parent 9eeea83701d86ff4312d309c9250f1faadaf6d8e

Renamed lvs guard to use_power_pins

- Also, added guard to the cells in the custom memory
- dropped DLVS from the dv Makefiles

verilog/rtl/caravel_clocking.v

diff --git a/verilog/rtl/caravel_clocking.v b/verilog/rtl/caravel_clocking.v
index ecf8215..1b1555f 100644
--- a/verilog/rtl/caravel_clocking.v
+++ b/verilog/rtl/caravel_clocking.v
@@ -1,7 +1,7 @@
 // This routine synchronizes the 
 
 module caravel_clocking(
-`ifdef LVS
+`ifdef USE_POWER_PINS
     input vdd1v8,
     input vss,
 `endif