Corrected the mess caused by introducing default_nettype none into the design
verification netlists. Also cleaned up the broken power-on-reset signaling,
and added connections from the user space to the I/O pad direct-to-pad analog
signal pins.
diff --git a/verilog/rtl/mgmt_protect.v b/verilog/rtl/mgmt_protect.v
index c5c79f3..ad25704 100644
--- a/verilog/rtl/mgmt_protect.v
+++ b/verilog/rtl/mgmt_protect.v
@@ -302,7 +302,7 @@
.VNB(vssd),
`endif
.A(mprj_vdd_logic1),
- .X(user_vdd_powergood)
+ .X(user1_vdd_powergood)
);
sky130_fd_sc_hd__buf_8 mprj2_vdd_pwrgood (
@@ -316,3 +316,4 @@
.X(user2_vdd_powergood)
);
endmodule
+`default_nettype wire
