Corrected the mess caused by introducing default_nettype none into the design
verification netlists. Also cleaned up the broken power-on-reset signaling,
and added connections from the user space to the I/O pad direct-to-pad analog
signal pins.
diff --git a/verilog/rtl/caravel_clocking.v b/verilog/rtl/caravel_clocking.v
index aa49d6f..4abdae9 100644
--- a/verilog/rtl/caravel_clocking.v
+++ b/verilog/rtl/caravel_clocking.v
@@ -20,6 +20,9 @@
);
wire pll_clk_sel;
+ wire pll_clk_divided;
+ wire pll_clk90_divided;
+ wire core_ext_clk;
reg use_pll_first;
reg use_pll_second;
reg ext_clk_syncd_pre;
@@ -90,3 +93,4 @@
assign resetb_sync = ~(reset_delay[0] | ext_reset);
endmodule
+`default_nettype wire
