commit 4903edb6f90332c3dc3a86cc27c7c2711386ae85
author Tonokip <tonokip@gmail.com> Wed Dec 16 16:59:28 2020 -0600
committer Tonokip <tonokip@gmail.com> Wed Dec 16 16:59:28 2020 -0600
tree 946b041effe56121116b78b36d294e73061ef8c5
parent 5ac99b67d25dafa1d29368de9429f45a870b1e29

fix Makefile to include testbench files

verilog/dv/caravel/user_proj_example/io_ports/Makefile

diff --git a/verilog/dv/caravel/user_proj_example/io_ports/Makefile b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
index 220a1d2..d8725d1 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/Makefile
+++ b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
@@ -22,7 +22,7 @@
 %.vvp: %_tb.v %.hex
 ifeq ($(SIM),RTL)
 	iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) -I $(RAPCORES_PATH)/.. -I $(RAPCORES_PATH)/src \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) -I $(RAPCORES_PATH)/.. -I $(RAPCORES_PATH)/src -I $(RAPCORES_PATH)/testbench \
 	-o $@ $<
 else 
 	iverilog -DPROJ_GL -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \