In spite of many errors that still need fixing, this is a major advance
over the previous commit. All verilog modules are in place more or less
as intended, with various functions such as the housekeeping SPI placed
on user area pads, with the ability to switch to user control from the
configuration. The pad control bits are local to the pads and loaded
via serial shift register, so that there are not hundreds of control wires
feeding into the user space. The user has three basic controls over each
pad: in, out, and outenb. Two timer/counters and an SPI master have been
added to the SoC. The SPI master shares I/O with the housekeeping SPI, so
that all housekeeping SPI registers can be accessed from the SoC directly.
diff --git a/verilog/rtl/sysctrl.v b/verilog/rtl/sysctrl.v
index 62ed4fc..86ec1e5 100644
--- a/verilog/rtl/sysctrl.v
+++ b/verilog/rtl/sysctrl.v
@@ -1,8 +1,8 @@
module sysctrl_wb #(
parameter BASE_ADR = 32'h2F00_0000,
- parameter PLL_OUT = 8'h0c,
- parameter TRAP_OUT = 8'h10,
- parameter IRQ7_SRC = 8'h14
+ parameter PLL_OUT = 8'h00,
+ parameter TRAP_OUT = 8'h04,
+ parameter IRQ7_SRC = 8'h08
) (
input wb_clk_i,
input wb_rst_i,
@@ -60,9 +60,9 @@
module sysctrl #(
parameter BASE_ADR = 32'h2300_0000,
- parameter PLL_OUT = 8'h0c,
- parameter TRAP_OUT = 8'h10,
- parameter IRQ7_SRC = 8'h14
+ parameter PLL_OUT = 8'h00,
+ parameter TRAP_OUT = 8'h04,
+ parameter IRQ7_SRC = 8'h08
) (
input clk,
input resetn,
