commit 41dbea2651596d9c76bd18cb9a13c472a3cfab0f
author johnnyr <johnny@ultimachine.com> Tue Dec 15 17:00:05 2020 -0600
committer johnnyr <johnny@ultimachine.com> Tue Dec 15 17:00:05 2020 -0600
tree 9b529f1afc7c8c15bd8b874c56afafc0a73e1f31
parent f5623a1422894f490f827d56db7f3659685f2577

fix oeb for updated pins

verilog/rtl/rapcore_caravel.v

diff --git a/verilog/rtl/rapcore_caravel.v b/verilog/rtl/rapcore_caravel.v
index c41a5e6..c1147f8 100644
--- a/verilog/rtl/rapcore_caravel.v
+++ b/verilog/rtl/rapcore_caravel.v
@@ -106,13 +106,13 @@
     assign io_oeb[17] = 1'b0;    // PHASE_B2_H
     assign io_oeb[18] = 1'b1;    // ENC_B
     assign io_oeb[19] = 1'b1;    // ENC_A
-    assign io_oeb[12] = 1'b0;    // BUFFER_DTR
+    assign io_oeb[37] = 1'b0;    // BUFFER_DTR
     assign io_oeb[24] = 1'b0;    // MOVE_DONE
     assign io_oeb[29] = 1'b1;    // HALT
-    assign io_oeb[10] = 1'b1;    // SCK
-    assign io_oeb[9] = 1'b1;     // CS
-    assign io_oeb[8] = 1'b1;     // COPI
-    assign io_oeb[11] = 1'b0;    // CIPO
+    assign io_oeb[35] = 1'b1;    // SCK
+    assign io_oeb[34] = 1'b1;     // CS
+    assign io_oeb[33] = 1'b1;     // COPI
+    assign io_oeb[36] = 1'b0;    // CIPO
     assign io_oeb[30] = 1'b0;    // STEPOUTPUT
     assign io_oeb[31] = 1'b0;    // DIROUTPUT
     assign io_oeb[32] = 1'b1;    // STEPINPUT