resync files with mpw-one-b
diff --git a/verilog/rtl/DFFRAM.v b/verilog/rtl/DFFRAM.v
index c6af2a6..b80677f 100644
--- a/verilog/rtl/DFFRAM.v
+++ b/verilog/rtl/DFFRAM.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
`ifndef USE_CUSTOM_DFFRAM
diff --git a/verilog/rtl/DFFRAMBB.v b/verilog/rtl/DFFRAMBB.v
index 712a253..22ab55e 100644
--- a/verilog/rtl/DFFRAMBB.v
+++ b/verilog/rtl/DFFRAMBB.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
/*
Building blocks for DFF based RAM compiler for SKY130A
diff --git a/verilog/rtl/README b/verilog/rtl/README
index bc1d751..f36a305 100644
--- a/verilog/rtl/README
+++ b/verilog/rtl/README
@@ -1,3 +1,21 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+
A quick documentation of the Caravel memory map and operation
---------------------------------------------------------------
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 08a6241..fa85ee2 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -1,4 +1,18 @@
// `default_nettype none
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
/*--------------------------------------------------------------*/
/* caravel, a project harness for the Google/SkyWater sky130 */
/* fabrication process and open source PDK */
@@ -35,29 +49,36 @@
`ifdef GL
`include "gl/mgmt_core.v"
+ `include "gl/digital_pll.v"
+ `include "gl/DFFRAM.v"
+ `include "gl/storage.v"
+ `include "gl/user_id_programming.v"
+ `include "gl/chip_io.v"
`else
`include "mgmt_soc.v"
`include "housekeeping_spi.v"
`include "caravel_clocking.v"
`include "mgmt_core.v"
+ `include "digital_pll.v"
+ `include "DFFRAM.v"
+ `include "DFFRAMBB.v"
+ `include "storage.v"
+ `include "user_id_programming.v"
+ `include "clock_div.v"
+ `include "storage_bridge_wb.v"
+ `include "mprj_io.v"
+ `include "chip_io.v"
`endif
-`include "digital_pll.v"
+`include "mprj_logic_high.v"
+`include "mprj2_logic_high.v"
+`include "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v"
`include "mgmt_protect.v"
`include "mgmt_protect_hv.v"
-`include "mprj_io.v"
-`include "chip_io.v"
-`include "user_id_programming.v"
`include "user_project_wrapper.v"
`include "gpio_control_block.v"
-`include "clock_div.v"
`include "simple_por.v"
-`include "storage_bridge_wb.v"
-`include "DFFRAM.v"
-`include "DFFRAMBB.v"
`include "sram_1rw1r_32_256_8_sky130.v"
-`include "storage.v"
-`include "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v"
/*------------------------------*/
/* Include user project here */
@@ -569,6 +590,9 @@
.mgmt_gpio_out({sdo_out, jtag_out}),
.mgmt_gpio_oeb({sdo_outenb, jtag_outenb}),
+ .one(),
+ .zero(),
+
// Serial data chain for pad configuration
.serial_data_in(gpio_serial_link_shifted[1:0]),
.serial_data_out(gpio_serial_link[1:0]),
@@ -593,6 +617,7 @@
.pad_gpio_in(mprj_io_in[1:0])
);
+ wire [`MPRJ_IO_PADS-1:2] one_loop;
gpio_control_block gpio_control_in [`MPRJ_IO_PADS-1:2] (
`ifdef USE_POWER_PINS
.vccd(vccd),
@@ -608,7 +633,10 @@
.mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-1):2]),
.mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS-1):2]),
- .mgmt_gpio_oeb(1'b1),
+ .mgmt_gpio_oeb(one_loop),
+
+ .one(one_loop),
+ .zero(),
// Serial data chain for pad configuration
.serial_data_in(gpio_serial_link_shifted[(`MPRJ_IO_PADS-1):2]),
@@ -638,8 +666,8 @@
.USER_PROJECT_ID(USER_PROJECT_ID)
) user_id_value (
`ifdef USE_POWER_PINS
- .vdd1v8(vccd),
- .vss(vssd),
+ .VPWR(vccd),
+ .VGND(vssd),
`endif
.mask_rev(mask_rev)
);
diff --git a/verilog/rtl/caravel_clocking.v b/verilog/rtl/caravel_clocking.v
index 4abdae9..cc0af25 100644
--- a/verilog/rtl/caravel_clocking.v
+++ b/verilog/rtl/caravel_clocking.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
// This routine synchronizes the
diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index bbc238d..850549f 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
// `default_nettype none
module chip_io(
// Package Pins
diff --git a/verilog/rtl/clock_div.v b/verilog/rtl/clock_div.v
index 6f898df..49ff44b 100644
--- a/verilog/rtl/clock_div.v
+++ b/verilog/rtl/clock_div.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
/* Integer-N clock divider */
`default_nettype none
diff --git a/verilog/rtl/convert_gpio_sigs.v b/verilog/rtl/convert_gpio_sigs.v
index 89ee8b5..e9e8351 100644
--- a/verilog/rtl/convert_gpio_sigs.v
+++ b/verilog/rtl/convert_gpio_sigs.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
/* Convert the standard set of GPIO signals: input, output, output_enb,
* pullup, and pulldown into the set needed by the s8 GPIO pads:
diff --git a/verilog/rtl/counter_timer_high.v b/verilog/rtl/counter_timer_high.v
index 2f1ea58..ea946f0 100755
--- a/verilog/rtl/counter_timer_high.v
+++ b/verilog/rtl/counter_timer_high.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
/* Simple 32-bit counter-timer for Caravel. */
diff --git a/verilog/rtl/counter_timer_low.v b/verilog/rtl/counter_timer_low.v
index fd94d2c..c543a6b 100755
--- a/verilog/rtl/counter_timer_low.v
+++ b/verilog/rtl/counter_timer_low.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
/* Simple 32-bit counter-timer for Caravel. */
diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v
index b9df2bd..3c9e595 100644
--- a/verilog/rtl/defines.v
+++ b/verilog/rtl/defines.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
// Global parameters
diff --git a/verilog/rtl/digital_pll.v b/verilog/rtl/digital_pll.v
index 9840a7d..b8dd69e 100644
--- a/verilog/rtl/digital_pll.v
+++ b/verilog/rtl/digital_pll.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
// Digital PLL (ring oscillator + controller)
// Technically this is a frequency locked loop, not a phase locked loop.
diff --git a/verilog/rtl/digital_pll_controller.v b/verilog/rtl/digital_pll_controller.v
index 0cd59b0..ae13d9d 100644
--- a/verilog/rtl/digital_pll_controller.v
+++ b/verilog/rtl/digital_pll_controller.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
// (True) digital PLL
//
diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v
index 9f9ac7a..f011e38 100644
--- a/verilog/rtl/gpio_control_block.v
+++ b/verilog/rtl/gpio_control_block.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
/*
*---------------------------------------------------------------------
@@ -80,7 +95,12 @@
output [2:0] pad_gpio_dm,
output pad_gpio_outenb,
output pad_gpio_out,
- input pad_gpio_in
+ input pad_gpio_in,
+
+ // to provide a way to automatically disable/enable output
+ // from the outside with needing a conb cell
+ output one,
+ output zero
);
/* Parameters defining the bit offset of each function in the chain */
@@ -122,6 +142,8 @@
wire pad_gpio_outenb;
wire pad_gpio_out;
wire pad_gpio_in;
+ wire one;
+ wire zero;
wire user_gpio_in;
wire gpio_in_unbuf;
@@ -195,9 +217,12 @@
/* Implement pad control behavior depending on state of mgmt_ena */
- assign gpio_in_unbuf = (mgmt_ena) ? 1'b0 : pad_gpio_in;
- assign mgmt_gpio_in = (mgmt_ena) ? ((gpio_inenb == 1'b0) ?
- pad_gpio_in : 1'bz) : 1'b0;
+// assign gpio_in_unbuf = (mgmt_ena) ? 1'b0 : pad_gpio_in;
+// assign mgmt_gpio_in = (mgmt_ena) ? ((gpio_inenb == 1'b0) ?
+// pad_gpio_in : 1'bz) : 1'b0;
+
+ assign gpio_in_unbuf = pad_gpio_in;
+ assign mgmt_gpio_in = (gpio_inenb == 1'b0) ? pad_gpio_in : 1'bz;
assign pad_gpio_outenb = (mgmt_ena) ? ((mgmt_gpio_oeb == 1'b1) ? gpio_outenb :
1'b0) : user_gpio_oeb;
@@ -232,5 +257,16 @@
.TE(gpio_logic1)
);
+ sky130_fd_sc_hd__conb_1 const_source (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .HI(one),
+ .LO(zero)
+ );
+
endmodule
`default_nettype wire
diff --git a/verilog/rtl/gpio_wb.v b/verilog/rtl/gpio_wb.v
index 70bf65e..9941fc9 100644
--- a/verilog/rtl/gpio_wb.v
+++ b/verilog/rtl/gpio_wb.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
module gpio_wb # (
parameter BASE_ADR = 32'h 2100_0000,
diff --git a/verilog/rtl/housekeeping_spi.v b/verilog/rtl/housekeeping_spi.v
index 7931d38..37c27c8 100644
--- a/verilog/rtl/housekeeping_spi.v
+++ b/verilog/rtl/housekeeping_spi.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
//-------------------------------------
// SPI controller for Caravel (PicoSoC)
diff --git a/verilog/rtl/la_wb.v b/verilog/rtl/la_wb.v
index 07dfc90..79a88a9 100644
--- a/verilog/rtl/la_wb.v
+++ b/verilog/rtl/la_wb.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
module la_wb # (
parameter BASE_ADR = 32'h 2200_0000,
diff --git a/verilog/rtl/manifest b/verilog/rtl/manifest
index f4886fb..a79b82a 100644
--- a/verilog/rtl/manifest
+++ b/verilog/rtl/manifest
@@ -1,5 +1,5 @@
b2feeb2a098894d5d731a5b011858a471e855d73 caravel_clocking.v
-8a0bcbd870778416bb4e753909053881aca2368a caravel.v
+c39b4f6a67a044aec105ca83ef1eb6d3f2b06028 caravel.v
38d2c674ea1f696bf2c9deaeee5f9b044f2445fb chip_io.v
d772308bd2a72121d7ed9dcdd40c8e6cbbe4b43c clock_div.v
f937b52e53d45bdbe41bcbd07c65b41104c21756 convert_gpio_sigs.v
@@ -9,20 +9,20 @@
d328f88dd48e015bbaa95e0d7c88954343cc5632 DFFRAM.v
ce49f9af199b5f16d2c39c417d58e5890bc7bab2 digital_pll_controller.v
fff2d08e49701312c2ebd6714b7425baf83f3d35 digital_pll.v
-e6902f7a9958eab32b8904c6f7e2d3c81be7766a gpio_control_block.v
+3588d4fbd0bd941be329ff0697ac2585e9036186 gpio_control_block.v
57554b3586f306944b31718a8c52526fa9a8a574 gpio_wb.v
baf3aba29655ca7021398ddc3f68be81eff0fa0c housekeeping_spi.v
0544035d9f2bfc52ebcb3220a21f29e98a3784b4 la_wb.v
ff3e65a783f3807340e25efac9207787d39fb6cd mem_wb.v
65feb79043201d3609307a3dd5af4e75cc26e81b mgmt_core.v
-f656dadb49cb97a46aada3d37a86a12f565e6e9e mgmt_protect_hv.v
-85dec445f0cf7afbef4aa6b919d31f0f5c9a0b7e mgmt_protect.v
+3b1ff20593bc386d13f5e2cf1571f08121889957 mgmt_protect_hv.v
+4d42909e102c472504739bc37559c6a34fd85ae1 mgmt_protect.v
20a482029168de93693a92ce03c00ec16e7b4776 mgmt_soc.v
+489b31e48e0ba327b6a70748fee664406c58f7a0 mprj2_logic_high.v
93eb7aa0f8489715145ff0870737fecf8be1fa8c mprj_ctrl.v
b16ace2e7a9c02ed5f8f918fe9e4a460422c7304 mprj_io.v
+98bd1d468969f47c370eb54ea8f178105953c8c9 mprj_logic_high.v
1352e5821905dce0b8203e9bee5e1adff02a9cbc pads.v
-5bcc269abdab76a7ddab2bee29f8032f97668043 parser.out
-b6e2bd2762a572fbf0f123412bfa7384827cc38b parsetab.py
5f1d9a90287fa5ae6635933c287e8e9e3e39931a picorv32.v
669d16642d5dd5f6824812754db20db98c9fe17b ring_osc2x13.v
6864cc10dacfd3edb4c66825b7a301ab097cea0d simple_por.v
diff --git a/verilog/rtl/mem_wb.v b/verilog/rtl/mem_wb.v
index 67e1f44..01bd2e1 100644
--- a/verilog/rtl/mem_wb.v
+++ b/verilog/rtl/mem_wb.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
module mem_wb (
`ifdef USE_POWER_PINS
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index cf2b996..dff9c0f 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
module mgmt_core (
`ifdef USE_POWER_PINS
diff --git a/verilog/rtl/mgmt_protect.v b/verilog/rtl/mgmt_protect.v
index 0c6840d..5220bce 100644
--- a/verilog/rtl/mgmt_protect.v
+++ b/verilog/rtl/mgmt_protect.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
/*----------------------------------------------------------------------*/
/* Buffers protecting the management region from the user region. */
@@ -80,26 +95,20 @@
wire [127:0] la_data_in_mprj_bar;
- sky130_fd_sc_hd__conb_1 mprj_logic_high [458:0] (
+ mprj_logic_high mprj_logic_high_inst (
`ifdef USE_POWER_PINS
- .VPWR(vccd1),
- .VGND(vssd1),
- .VPB(vccd1),
- .VNB(vssd1),
+ .vccd1(vccd1),
+ .vssd1(vssd1),
`endif
- .HI(mprj_logic1),
- .LO()
+ .HI(mprj_logic1)
);
- sky130_fd_sc_hd__conb_1 mprj2_logic_high (
+ mprj2_logic_high mprj2_logic_high_inst (
`ifdef USE_POWER_PINS
- .VPWR(vccd2),
- .VGND(vssd2),
- .VPB(vccd2),
- .VNB(vssd2),
+ .vccd2(vccd2),
+ .vssd2(vssd2),
`endif
- .HI(mprj2_logic1),
- .LO()
+ .HI(mprj2_logic1)
);
// Logic high in the VDDA (3.3V) domains
@@ -315,7 +324,7 @@
.VPB(vccd),
.VNB(vssd),
`endif
- .A(mprj2_vdd_logic1),
+ .A(mprj2_logic1),
.X(user2_vcc_powergood)
);
diff --git a/verilog/rtl/mgmt_protect_hv.v b/verilog/rtl/mgmt_protect_hv.v
index dbd04bb..23d9cf6 100644
--- a/verilog/rtl/mgmt_protect_hv.v
+++ b/verilog/rtl/mgmt_protect_hv.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
/*----------------------------------------------------------------------*/
/* mgmt_protect_hv: */
@@ -27,6 +42,13 @@
wire mprj_vdd_logic1_h;
wire mprj2_vdd_logic1_h;
+`ifdef USE_POWER_PINS
+ // This is to emulate the substrate shorting grounds together for LVS
+ // purposes
+ assign vssa2 = vssa1;
+ assign vssa1 = vssd;
+`endif
+
// Logic high in the VDDA (3.3V) domains
sky130_fd_sc_hvl__conb_1 mprj_logic_high_hvl (
@@ -76,6 +98,6 @@
.X(mprj2_vdd_logic1),
.A(mprj2_vdd_logic1_h)
);
-
endmodule
+
`default_nettype wire
diff --git a/verilog/rtl/mprj_ctrl.v b/verilog/rtl/mprj_ctrl.v
index b31c23a..d5c24bf 100644
--- a/verilog/rtl/mprj_ctrl.v
+++ b/verilog/rtl/mprj_ctrl.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
module mprj_ctrl_wb #(
parameter BASE_ADR = 32'h 2300_0000,
diff --git a/verilog/rtl/mprj_io.v b/verilog/rtl/mprj_io.v
index ad59c18..8e7a669 100644
--- a/verilog/rtl/mprj_io.v
+++ b/verilog/rtl/mprj_io.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
// `default_nettype none
module mprj_io #(
parameter AREA1PADS = 18 // Highest numbered pad in area 1
diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v
index 0e914b6..a523518 100644
--- a/verilog/rtl/pads.v
+++ b/verilog/rtl/pads.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
// `default_nettype none
`ifndef TOP_ROUTING
`define USER1_ABUTMENT_PINS \
diff --git a/verilog/rtl/ring_osc2x13.v b/verilog/rtl/ring_osc2x13.v
index 324c2c7..f20110e 100644
--- a/verilog/rtl/ring_osc2x13.v
+++ b/verilog/rtl/ring_osc2x13.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
// Tunable ring oscillator---synthesizable (physical) version.
//
diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
index 7fef90d..8168c0b 100644
--- a/verilog/rtl/simple_por.v
+++ b/verilog/rtl/simple_por.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
`timescale 1 ns / 1 ps
diff --git a/verilog/rtl/simple_spi_master.v b/verilog/rtl/simple_spi_master.v
index 4576925..c319de8 100755
--- a/verilog/rtl/simple_spi_master.v
+++ b/verilog/rtl/simple_spi_master.v
@@ -1,4 +1,18 @@
`default_nettype none
+// SPDX-FileCopyrightText: 2019 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
//----------------------------------------------------------------------------
// Module: simple_spi_master
//
diff --git a/verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v b/verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
index f992c1e..a746169 100644
--- a/verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
+++ b/verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped (
X ,
A ,
diff --git a/verilog/rtl/sram_1rw1r_32_256_8_sky130.v b/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
index afbfa12..f622079 100644
--- a/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
+++ b/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
// OpenRAM SRAM model
// Words: 256
diff --git a/verilog/rtl/storage.v b/verilog/rtl/storage.v
index a290525..2efacb8 100644
--- a/verilog/rtl/storage.v
+++ b/verilog/rtl/storage.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
module storage (
diff --git a/verilog/rtl/storage_bridge_wb.v b/verilog/rtl/storage_bridge_wb.v
index bf70052..0f24321 100644
--- a/verilog/rtl/storage_bridge_wb.v
+++ b/verilog/rtl/storage_bridge_wb.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
module storage_bridge_wb (
// MGMT_AREA R/W WB Interface
diff --git a/verilog/rtl/sysctrl.v b/verilog/rtl/sysctrl.v
index 7f11f75..c18979e 100644
--- a/verilog/rtl/sysctrl.v
+++ b/verilog/rtl/sysctrl.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
module sysctrl_wb #(
parameter BASE_ADR = 32'h2F00_0000,
diff --git a/verilog/rtl/user_id_programming.v b/verilog/rtl/user_id_programming.v
index 934f9d7..873bbce 100644
--- a/verilog/rtl/user_id_programming.v
+++ b/verilog/rtl/user_id_programming.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
// This module represents an unprogrammed mask revision
// block that is configured with via programming on the
@@ -8,8 +23,8 @@
parameter [ 0:0] USER_PROJECT_ID = 32'h0
) (
`ifdef USE_POWER_PINS
- inout vdd1v8,
- inout vss,
+ inout VPWR,
+ inout VGND,
`endif
output [31:0] mask_rev
);
@@ -21,10 +36,10 @@
sky130_fd_sc_hd__conb_1 mask_rev_value [31:0] (
`ifdef USE_POWER_PINS
- .VPWR(vdd1v8),
- .VPB(vdd1v8),
- .VNB(vss),
- .VGND(vss),
+ .VPWR(VPWR),
+ .VPB(VPWR),
+ .VNB(VGND),
+ .VGND(VGND),
`endif
.HI(user_proj_id_high),
.LO(user_proj_id_low)
diff --git a/verilog/rtl/wb_intercon.v b/verilog/rtl/wb_intercon.v
index 6c3ab52..7ebce83 100644
--- a/verilog/rtl/wb_intercon.v
+++ b/verilog/rtl/wb_intercon.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
`default_nettype none
module wb_intercon #(
parameter DW = 32, // Data Width
