commit 34fa3d15b40854a13e662b1c66344a40f0c73599
author johnnyr <johnny@ultimachine.com> Sat Dec 19 00:30:36 2020 -0600
committer johnnyr <johnny@ultimachine.com> Sat Dec 19 00:30:36 2020 -0600
tree 1a4ba2c01ccd5412eb215285ae4cf66a1142c8a1
parent 5906a0fe2d4d6cd059fbff9389800609cd29c9ef

missing mprj2 file

verilog/rtl/mprj2_logic_high.v

diff --git a/verilog/rtl/mprj2_logic_high.v b/verilog/rtl/mprj2_logic_high.v
new file mode 100644
index 0000000..f57f173
--- /dev/null
+++ b/verilog/rtl/mprj2_logic_high.v
@@ -0,0 +1,18 @@
+module mprj2_logic_high (
+`ifdef USE_POWER_PINS
+    inout	   vccd2,
+    inout	   vssd2,
+`endif
+    output         HI
+);
+sky130_fd_sc_hd__conb_1 inst (
+`ifdef USE_POWER_PINS
+                .VPWR(vccd2),
+                .VGND(vssd2),
+                .VPB(vccd2),
+                .VNB(vssd2),
+`endif
+                .HI(HI),
+                .LO()
+        );
+endmodule