Added two additional features: (1) Timer chaining, which allows one
timer to be clocked from the output of the other, forming a 64-bit
timer, and (2) User power-good signal, memory-mapped so that the state
of the user's 1.8V power domain can be assessed (should have the same
for the 3.3V domains). Also: The routing of the PLL output and trap
and IRQ inputs was moved from the single gpio pin to additional bits
in the user space, and an additional output routing was made for the
secondary clock.
diff --git a/verilog/rtl/mgmt_protect.v b/verilog/rtl/mgmt_protect.v
index 8865ee4..df32f81 100644
--- a/verilog/rtl/mgmt_protect.v
+++ b/verilog/rtl/mgmt_protect.v
@@ -18,6 +18,8 @@
inout vssd,
inout vccd1,
inout vssd1,
+ inout vccd2,
+ inout vssd2,
input caravel_clk,
input caravel_clk2,
@@ -40,12 +42,17 @@
output [3:0] mprj_sel_o_user,
output [31:0] mprj_adr_o_user,
output [31:0] mprj_dat_o_user,
- output [127:0] la_data_in_mprj
+ output [127:0] la_data_in_mprj,
+ output user1_powergood,
+ output user2_powergood
);
- wire [73:0] mprj_logic1;
+ wire [74:0] mprj_logic1;
+ wire mprj2_logic1;
+ wire user1_powergood;
+ wire user2_powergood;
- sky130_fd_sc_hd__conb_1 mprj_logic_high [73:0] (
+ sky130_fd_sc_hd__conb_1 mprj_logic_high [74:0] (
.VPWR(vccd1),
.VGND(vssd1),
.VPB(vccd1),
@@ -54,6 +61,16 @@
.LO()
);
+ sky130_fd_sc_hd__conb_1 mprj2_logic_high (
+ .VPWR(vccd2),
+ .VGND(vssd2),
+ .VPB(vccd2),
+ .VNB(vssd2),
+ .HI(mprj2_logic1),
+ .LO()
+ );
+
+
sky130_fd_sc_hd__einvp_8 mprj_rstn_buf (
.VPWR(vccd),
.VGND(vssd),
@@ -160,4 +177,26 @@
.TE(~la_oen)
);
+ /* The conb cell output is a resistive connection directly to */
+ /* the power supply, so when returning the user1_powergood */
+ /* signal, make sure that it is buffered properly. */
+
+ sky130_fd_sc_hd__buf_8 mprj_pwrgood (
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+ .A(mprj_logic1[74]),
+ .X(user1_powergood)
+ );
+
+ sky130_fd_sc_hd__buf_8 mprj2_pwrgood (
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+ .A(mprj_logic2),
+ .X(user2_powergood)
+ );
+
endmodule
