Add a global defines.v and rely less on parameters
- This is mainly to avoid "accidents" with default parameter values
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index d010e77..a72d99e 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -20,8 +20,6 @@
*/
module user_proj_example #(
- parameter IO_PADS = 38,
- parameter PWR_PADS = 4,
parameter BITS = 32
)(
inout vdda1, // User area 1 3.3V supply
@@ -51,16 +49,16 @@
input [127:0] la_oen,
// IOs
- input [IO_PADS-1:0] io_in,
- output [IO_PADS-1:0] io_out,
- output [IO_PADS-1:0] io_oeb
+ input [`MPRJ_IO_PADS-1:0] io_in,
+ output [`MPRJ_IO_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-1:0] io_oeb
);
wire clk;
wire rst;
- wire [IO_PADS-1:0] io_in;
- wire [IO_PADS-1:0] io_out;
- wire [IO_PADS-1:0] io_oeb;
+ wire [`MPRJ_IO_PADS-1:0] io_in;
+ wire [`MPRJ_IO_PADS-1:0] io_out;
+ wire [`MPRJ_IO_PADS-1:0] io_oeb;
wire [31:0] rdata;
wire [31:0] wdata;
@@ -78,7 +76,7 @@
// IO
assign io_out = count;
- assign io_oeb = {(IO_PADS-1){rst}};
+ assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
// LA
assign la_data_out = {{(127-BITS){1'b0}}, count};
