changes that got DRC=17
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
deleted file mode 120000
index d4a8f25..0000000
--- a/openlane/user_project_wrapper/config.tcl
+++ /dev/null
@@ -1 +0,0 @@
-../user_project_wrapper_empty/config.tcl
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
new file mode 100644
index 0000000..fc75c08
--- /dev/null
+++ b/openlane/user_project_wrapper/config.tcl
@@ -0,0 +1,59 @@
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) user_project_wrapper
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+set ::env(PDN_CFG) $script_dir/pdn.tcl
+set ::env(FP_PDN_CORE_RING) 1
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2920 3520"
+
+set ::env(DESIGN_IS_CORE) 1
+#set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+
+set ::unit 2.4
+set ::env(FP_IO_VEXTEND) [expr 2*$::unit]
+set ::env(FP_IO_HEXTEND) [expr 2*$::unit]
+set ::env(FP_IO_VLENGTH) $::unit
+set ::env(FP_IO_HLENGTH) $::unit
+
+set ::env(FP_IO_VTHICKNESS_MULT) 4
+set ::env(FP_IO_HTHICKNESS_MULT) 4
+
+set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_PERIOD) "15"
+
+set ::env(CLOCK_PORT) "user_clock2"
+set ::env(CLOCK_NET) "mprj.clk"
+
+set ::env(CLOCK_PERIOD) "10"
+
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
+set ::env(DIODE_INSERTION_STRATEGY) 3
+
+set ::env(ROUTING_CORES) 6
+
+# Need to fix a FastRoute bug for this to work, but it's good
+# for a sense of "isolation"
+set ::env(MAGIC_ZEROIZE_ORIGIN) 0
+set ::env(MAGIC_WRITE_FULL_LEF) 1
+
+set ::env(VERILOG_FILES) "\
+ $script_dir/../../verilog/rtl/defines.v \
+ $script_dir/../../verilog/rtl/user_project_wrapper.v"
+
+set ::env(VERILOG_FILES_BLACKBOX) "\
+ $script_dir/../../verilog/rtl/defines.v \
+ $script_dir/../../rapcore_caravel_defines.v \
+ $script_dir/../../rapcores/src/macro_params.v \
+ $script_dir/../../rapcores/src/constants.v \
+ $script_dir/../../rapcores/src/rapcore.v"
+
+set ::env(EXTRA_LEFS) "\
+ $script_dir/../../lef/rapcore.lef"
+
+set ::env(EXTRA_GDS_FILES) "\
+ $script_dir/../../gds/rapcore.gds"
+
+#set ::env(GLB_RT_OBS) "met4 1150 1700 1690 2240"
+
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
index d731d3c..8a711ed 100644
--- a/openlane/user_project_wrapper/interactive.tcl
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -10,25 +10,26 @@
place_io_ol
-set ::env(FP_DEF_TEMPATE) $script_dir/../../def/user_project_wrapper_empty.def
+#set ::env(FP_DEF_TEMPLATE) $script_dir/../../def/user_project_wrapper_empty.def
-apply_def_template
+#apply_def_template
add_macro_placement rapcore 1150 1700 N
manual_macro_placement f
-set ::env(_SPACING) 1.6
+set ::env(_SPACING) 1.62
set ::env(_WIDTH) 3
-set power_domains [list {vccd1 vssd1} {vccd2 vssd2} {vdda1 vssa1} {vdda2 vssa2}]
+#set power_domains [list {vccd1 vssd1} {vccd2 vssd2} {vdda1 vssa1} {vdda2 vssa2}]
+set power_domains [list {vccd1 vssd1} ]
set ::env(_VDD_NET_NAME) vccd1
set ::env(_GND_NET_NAME) vssd1
set ::env(_V_OFFSET) 14
set ::env(_H_OFFSET) $::env(_V_OFFSET)
-set ::env(_V_PITCH) 180
-set ::env(_H_PITCH) 180
+set ::env(_V_PITCH) 153.6
+set ::env(_H_PITCH) 153.18
set ::env(_V_PDN_OFFSET) 0
set ::env(_H_PDN_OFFSET) 0
