Add two more missing USE_POWER_PINS guards
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 10c054a..abe18bf 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -436,6 +436,7 @@
/* the vccd1 domain. */
mgmt_protect mgmt_buffers (
+ `ifdef USE_POWER_PINS
.vccd(vccd),
.vssd(vssd),
.vccd1(vccd1),
@@ -444,6 +445,7 @@
.vssa1(vssa1),
.vdda2(vdda2),
.vssa2(vssa2),
+ `endif
.caravel_clk(caravel_clk),
.caravel_clk2(caravel_clk2),
@@ -483,6 +485,7 @@
/*----------------------------------------------*/
user_project_wrapper mprj (
+ `ifdef USE_POWER_PINS
.vdda1(vdda1), // User area 1 3.3V power
.vdda2(vdda2), // User area 2 3.3V power
.vssa1(vssa1), // User area 1 analog ground
@@ -491,6 +494,7 @@
.vccd2(vccd2), // User area 2 1.8V power
.vssd1(vssd1), // User area 1 digital ground
.vssd2(vssd2), // User area 2 digital ground
+ `endif
.wb_clk_i(mprj_clock),
.wb_rst_i(mprj_reset),
diff --git a/verilog/rtl/mgmt_protect.v b/verilog/rtl/mgmt_protect.v
index d285a91..0c6840d 100644
--- a/verilog/rtl/mgmt_protect.v
+++ b/verilog/rtl/mgmt_protect.v
@@ -15,6 +15,7 @@
/*----------------------------------------------------------------------*/
module mgmt_protect (
+`ifdef USE_POWER_PINS
inout vccd,
inout vssd,
inout vccd1,
@@ -25,6 +26,7 @@
inout vssa1,
inout vdda2,
inout vssa2,
+`endif
input caravel_clk,
input caravel_clk2,
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index b5460f5..48220b1 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -17,6 +17,7 @@
module user_project_wrapper #(
parameter BITS = 32
)(
+`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
@@ -25,6 +26,7 @@
inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground
+`endif
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
