[Docs]: WIP how to run documentation -- rev. 1
diff --git a/README.md b/README.md
index cffca22..3e002ed 100644
--- a/README.md
+++ b/README.md
@@ -20,23 +20,52 @@
- Aboard Caravel -- How to put your design on Caravel? -- https://youtu.be/9QV8SDelURk
- Things to Clarify About Caravel -- What versions to use with Caravel? -- https://youtu.be/-LZ522mxXMw
+## Aboard Caravel:
+### Versions:
+- [OpenLANE](https://github.com/efabless/openlane) rc4 or rc5.
+- latest [Skywater-pdk](https://github.com/google/skywater-pdk).
+ - sky130_fd_sc_hd
+ - sky130_fd_sc_hvl
+ - sky130_fd_io
+- latest [open_pdks](https://github.com/RTimothyEdwards/open_pdks).
+
+Your area is the full user_project_wrapper, so feel free to add your project there or create a differnt macro and harden it seperately then insert it into the user_project_wrapper.
+
+If you will use OpenLANE to harden your design, go through the instructions in this [README.md][0].
+
+Then, you will need to put your design aboard the Caravel chip. In the Caravel directory, make sure you have the following:
+
+- Magic installed on your machine. We may provide a Dockerized version later.
+- You have your user_project_wrapper.gds under `./gds/` directory.
+
+Run the following command:
+
+```bash
+export PDK_ROOT=<The place where the installed pdk resides>
+make
+```
+
+This should merge the GDSes using magic and you'll end up with your version of `./gds/caravel.gds`.
+
## Managment SoC
The managment SoC runs firmware that can be used to:
-- Configure Mega Project I/O pads
-- Observe and control Mega Project signals (through on-chip logic analyzer probes)
-- Control the Mega Project power supply
+- Configure User Project I/O pads
+- Observe and control User Project signals (through on-chip logic analyzer probes)
+- Control the User Project power supply
The memory map of the management SoC can be found [here](verilog/rtl/README)
-## Mega Project Area
+## User Project Area
This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See [the Caravel premliminary datasheet](doc/caravel_datasheet.pdf) for details.
-The repository contains a [sample mega project](/verilog/rtl/user_proj_example.v) that contains a binary 32-bit up counter. </br>
+The repository contains a [sample user project](/verilog/rtl/user_proj_example.v) that contains a binary 32-bit up counter. </br>
<p align=”center”>
<img src="/doc/counter_32.png" width="50%" height="50%">
</p>
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:
-1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: [IO_Ports Test](verilog/dv/caravel/user_proj_example/io_ports).
-2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: [LA_Test1](verilog/dv/caravel/user_proj_example/la_test1).
-3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: [LA_Test2](verilog/dv/caravel/user_proj_example/la_test2).
+1. Configure the User Project I/O pads as o/p. Observe the counter value in the testbench: [IO_Ports Test](verilog/dv/caravel/user_proj_example/io_ports).
+2. Configure the User Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: [LA_Test1](verilog/dv/caravel/user_proj_example/la_test1).
+3. Configure the User Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: [LA_Test2](verilog/dv/caravel/user_proj_example/la_test2).
+
+[0]: openlane/README.md
