commit cd4cff7247745cbfba442ae715685276b68c45a8
author Manar <manarabdelatty@aucegypt.edu> Wed Nov 04 16:22:59 2020 +0200
committer Manar <manarabdelatty@aucegypt.edu> Wed Nov 04 16:22:59 2020 +0200
tree f3d30f6fe89740d77650b25bea54a645f7c471a2
parent f8e6154eaeecd6d6edcfa19cda6a64cdd2f2db5d

Connected WB MI A port outputs to the wb bus

verilog/rtl/mgmt_soc.v

diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index 8235436..cf0793d 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -681,6 +681,13 @@
         .la_oen(la_oen)
     );
     
+    // User project WB MI A port
+    assign mprj_cyc_o = cpu_cyc_o;
+    assign mprj_we_o  = cpu_we_o;
+    assign mprj_sel_o = cpu_sel_o;
+    assign mprj_adr_o = cpu_adr_o;
+    assign mprj_dat_o = cpu_dat_o;
+
     // WB Slave User Project Control
     wire mprj_ctrl_stb_i;
     wire mprj_ctrl_ack_o;