blob: 50e0bd1767f52a08b4438cabce8ccd653db409fc [file] [log] [blame]
set script_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) user_project_wrapper
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
set ::env(CLOCK_PORT) "user_clock2"
set ::env(CLOCK_NET) "mprj.clk"
set ::env(CLOCK_PERIOD) "10"
set ::env(FP_PDN_CORE_RING) 1
set ::env(PDN_CFG) $script_dir/pdn.tcl
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 2920 3520"
set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
set ::env(DIODE_INSERTION_STRATEGY) 0
set ::env(VERILOG_FILES) "\
$script_dir/../../verilog/rtl/defines.v \
$script_dir/../../verilog/rtl/user_project_wrapper.v"
set ::env(VERILOG_FILES_BLACKBOX) "\
$script_dir/../../verilog/rtl/defines.v \
$script_dir/../../verilog/rtl/user_proj_example.v"
set ::env(EXTRA_LEFS) "\
$script_dir/../../lef/user_proj_example.lef"
set ::env(EXTRA_GDS_FILES) "\
$script_dir/../../gds/user_proj_example.gds"