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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-009 / 907394669505129b4a7baf4fb8236313fc552af3
commit907394669505129b4a7baf4fb8236313fc552af3[log] [tgz]
authorTim Edwards <tim@opencircuitdesign.com>Fri Oct 09 22:15:28 2020 -0400
committerTim Edwards <tim@opencircuitdesign.com>Fri Oct 09 22:15:28 2020 -0400
tree9ee29cf037b49ccffa25ed26cf9b7156e5ec4707
parentbb3cd69b4ddc706fd7c4f828fb85044152a6bbc5 [diff]
Removed a small error in the PLL testbench C code.  However, the
PLL testbench drives the CPU into the trap state, and it is not
obvious why.
1 file changed
tree: 9ee29cf037b49ccffa25ed26cf9b7156e5ec4707
  1. doc/
  2. verilog/
  3. README.md
README.md

CIIC Harness (Phase 1)

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Managment SoC

The managment SoC runs firmware taht can be used to:

  • Configure Mega Project I/O pads
  • Observe and control Mega Project signals (through on-chip logic analyzer probes)
  • Control the Mega Project power supply

The memory map of the management SoC is given below

Mega Project Area

This is the user space. It has limitted silicon area (???) as well as a fixed number of I/O pads (???). The repoo contains a sample mega project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

  1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
  2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
  3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.