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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-009 / 5ae07d9b4afeab093f9da812ec8cc29a1d800dbb
commit5ae07d9b4afeab093f9da812ec8cc29a1d800dbb[log] [tgz]
authorTim Edwards <tim@opencircuitdesign.com>Thu Oct 08 22:10:00 2020 -0400
committerTim Edwards <tim@opencircuitdesign.com>Thu Oct 08 22:10:00 2020 -0400
tree2068a7ecbb70347a57d7aee6b66c77c4356fb193
parent9eda80dd074325b1d42354785b1aece24ce83017 [diff]
Corrected the error causing the failure of the GPIO testbench.
Now it only remains to update the other testbenches with the
correct pin names for all the voltage domains.
1 file changed
tree: 2068a7ecbb70347a57d7aee6b66c77c4356fb193
  1. doc/
  2. verilog/
  3. README.md
README.md

CIIC Harness (Phase 1)

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Managment SoC

The managment SoC runs firmware taht can be used to:

  • Configure Mega Project I/O pads
  • Observe and control Mega Project signals (through on-chip logic analyzer probes)
  • Control the Mega Project power supply

The memory map of the management SoC is given below

Mega Project Area

This is the user space. It has limitted silicon area (???) as well as a fixed number of I/O pads (???). The repoo contains a sample mega project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

  1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
  2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
  3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.