Corrections to the management protection buffer block, and a couple of corrections to errors in the testbenchs for io_ports and la_test1. Applying updates to the management protection block that I made to the release branch after it was frozen.
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v index 153e704..85d2d17 100644 --- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v +++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -91,6 +91,8 @@ wire flash_io0; wire flash_io1; + wire USER_VDD1V8; + wire USER_VDD3V3; wire VDD1V8; wire VDD3V3; wire VSS;
diff --git a/verilog/dv/caravel/user_proj_example/la_test1/la_test1.hex b/verilog/dv/caravel/user_proj_example/la_test1/la_test1.hex new file mode 100755 index 0000000..5dfca2f --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/la_test1/la_test1.hex
@@ -0,0 +1,75 @@ +@00000000 +93 00 00 00 93 01 00 00 13 02 00 00 93 02 00 00 +13 03 00 00 93 03 00 00 13 04 00 00 93 04 00 00 +13 05 00 00 93 05 00 00 13 06 00 00 93 06 00 00 +13 07 00 00 93 07 00 00 13 08 00 00 93 08 00 00 +13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00 +13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00 +13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00 +13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 C5 41 +93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1 +11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 00 00 +63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 11 22 +01 A0 01 00 B7 02 00 28 13 03 00 12 23 90 62 00 +A3 81 02 00 05 C6 21 4F 93 73 F6 0F 93 DE 73 00 +23 80 D2 01 93 EE 0E 01 23 80 D2 01 86 03 93 F3 +F3 0F 7D 1F E3 14 0F FE 23 80 62 00 A1 C9 13 0F +00 02 83 23 05 00 A1 4F 93 DE F3 01 23 80 D2 01 +93 EE 0E 01 23 80 D2 01 83 CE 02 00 93 FE 2E 00 +93 DE 1E 00 86 03 B3 E3 D3 01 7D 1F 63 17 0F 00 +23 20 75 00 11 05 83 23 05 00 FD 1F E3 96 0F FC +FD 15 F1 F1 63 04 0F 00 23 20 75 00 13 03 00 08 +A3 81 62 00 82 80 01 00 00 00 01 11 06 CE 22 CC +00 10 AA 87 A3 07 F4 FE 03 47 F4 FE A9 47 63 14 +F7 00 35 45 DD 37 B7 07 00 20 91 07 03 47 F4 FE +98 C3 01 00 F2 40 62 44 05 61 82 80 01 11 06 CE +22 CC 00 10 23 26 A4 FE 19 A8 83 27 C4 FE 13 87 +17 00 23 26 E4 FE 83 C7 07 00 3E 85 7D 37 83 27 +C4 FE 83 C7 07 00 F5 F3 01 00 F2 40 62 44 05 61 +82 80 41 11 06 C6 22 C4 00 08 B7 07 00 26 93 87 +C7 09 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +87 09 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +47 09 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +07 09 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +C7 08 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +87 08 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +47 08 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +07 08 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +C7 07 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +87 07 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +47 07 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +07 07 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +C7 06 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +87 06 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +47 06 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +07 06 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 +C7 05 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +87 05 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +47 05 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +07 05 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +C7 04 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +87 04 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +47 04 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +07 04 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +C7 03 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +47 03 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +07 03 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +C7 02 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +87 02 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +47 02 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +07 02 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 +87 03 09 67 13 07 97 80 98 C3 B7 07 00 20 13 07 +10 27 98 C3 B7 07 00 20 A1 07 05 47 98 C3 B7 07 +00 26 05 47 98 C3 01 00 B7 07 00 26 98 43 85 47 +E3 0C F7 FE B7 07 00 25 C1 07 7D 57 98 C3 B7 07 +00 25 D1 07 23 A0 07 00 B7 07 00 25 E1 07 7D 57 +98 C3 B7 07 00 25 F1 07 7D 57 98 C3 B7 07 00 26 +A1 07 37 07 40 AB 98 C3 B7 07 00 25 91 07 23 A0 +07 00 B7 07 00 25 D1 07 7D 57 98 C3 B7 07 00 25 +98 43 93 07 40 1F E3 FB E7 FE B7 07 00 26 A1 07 +37 07 41 AB 98 C3 01 00 B7 07 00 10 13 85 47 47 +35 33 B7 07 00 10 13 85 87 47 0D 33 B7 07 00 26 +A1 07 37 07 51 AB 98 C3 01 00 B2 40 22 44 41 01 +82 80 00 00 0A 00 00 00 4D 6F 6E 69 74 6F 72 3A +20 54 65 73 74 20 32 20 50 61 73 73 65 64 0A 0A +00 00 00 00
diff --git a/verilog/dv/caravel/user_proj_example/la_test2/Makefile b/verilog/dv/caravel/user_proj_example/la_test2/Makefile index 874bed5..396a385 100644 --- a/verilog/dv/caravel/user_proj_example/la_test2/Makefile +++ b/verilog/dv/caravel/user_proj_example/la_test2/Makefile
@@ -25,18 +25,22 @@ %.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s <<<<<<< HEAD +<<<<<<< HEAD ${GCC_PATH}/${GCC_PREFIX}-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< ======= ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< >>>>>>> 6000cbf... Updates to the Makefiles for easier passing of user-specific variables, +======= + ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< +>>>>>>> 9bc2778... Corrections to the management protection buffer block, and a couple of corrections %.hex: %.elf - ${GCC_PATH}/${GCC_PREFIX}-unknown-elf-objcopy -O verilog $< $@ + ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ # to fix flash base address sed -i 's/@10000000/@00000000/g' $@ %.bin: %.elf - ${GCC_PATH}/${GCC_PREFIX}-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ # ---- Clean ----
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index 95ca327..3832f67 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v
@@ -293,12 +293,13 @@ wire [7:0] spi_ro_config_core; // LA signals - wire [127:0] la_output_core; // From CPU to MPRJ - wire [127:0] la_data_in_mprj; // From CPU to MPRJ + wire [127:0] la_data_in_user; // From CPU to MPRJ + wire [127:0] la_data_in_mprj; // From MPRJ to CPU wire [127:0] la_data_out_mprj; // From CPU to MPRJ - wire [127:0] la_output_mprj; // From MPRJ to CPU - wire [127:0] la_oen; // LA output enable from CPU perspective (active-low) - + wire [127:0] la_data_out_user; // From MPRJ to CPU + wire [127:0] la_oen_user; // From CPU to MPRJ + wire [127:0] la_oen_mprj; // From CPU to MPRJ + // WB MI A (User Project) wire mprj_cyc_o_core; wire mprj_stb_o_core; @@ -386,9 +387,9 @@ .user_clk(caravel_clk2), .core_rstn(caravel_rstn), // Logic Analyzer - .la_input(la_data_out_mprj), - .la_output(la_output_core), - .la_oen(la_oen), + .la_input(la_data_in_mprj), + .la_output(la_data_out_mprj), + .la_oen(la_oen_mprj), // User Project IO Control .mprj_vcc_pwrgood(mprj_vcc_pwrgood), .mprj2_vcc_pwrgood(mprj2_vcc_pwrgood), @@ -452,8 +453,12 @@ .mprj_sel_o_core(mprj_sel_o_core), .mprj_adr_o_core(mprj_adr_o_core), .mprj_dat_o_core(mprj_dat_o_core), - .la_output_core(la_output_core), - .la_oen(la_oen), + .la_data_out_core(la_data_out_user), + .la_data_out_mprj(la_data_out_mprj), + .la_data_in_core(la_data_in_user), + .la_data_in_mprj(la_data_in_mprj), + .la_oen_mprj(la_oen_mprj), + .la_oen_core(la_oen_user), .user_clock(mprj_clock), .user_clock2(mprj_clock2), @@ -465,7 +470,6 @@ .mprj_sel_o_user(mprj_sel_o_user), .mprj_adr_o_user(mprj_adr_o_user), .mprj_dat_o_user(mprj_dat_o_user), - .la_data_in_mprj(la_data_in_mprj), .user1_vcc_powergood(mprj_vcc_pwrgood), .user2_vcc_powergood(mprj2_vcc_pwrgood), .user1_vdd_powergood(mprj_vdd_pwrgood), @@ -499,9 +503,9 @@ .wbs_ack_o(mprj_ack_i_core), .wbs_dat_o(mprj_dat_i_core), // Logic Analyzer - .la_data_in(la_data_in_mprj), - .la_data_out(la_data_out_mprj), - .la_oen (la_oen), + .la_data_in(la_data_in_user), + .la_data_out(la_data_out_user), + .la_oen(la_oen_user), // IO Pads .io_in (user_io_in), .io_out(user_io_out),
diff --git a/verilog/rtl/mgmt_protect.v b/verilog/rtl/mgmt_protect.v index ad25704..563510b 100644 --- a/verilog/rtl/mgmt_protect.v +++ b/verilog/rtl/mgmt_protect.v
@@ -35,8 +35,17 @@ input [3:0] mprj_sel_o_core, input [31:0] mprj_adr_o_core, input [31:0] mprj_dat_o_core, - input [127:0] la_output_core, - input [127:0] la_oen, + + // All signal in/out directions are the reverse of the signal + // names at the buffer intrface. + + output [127:0] la_data_in_mprj, + input [127:0] la_data_out_mprj, + input [127:0] la_oen_mprj, + + input [127:0] la_data_out_core, + output [127:0] la_data_in_core, + output [127:0] la_oen_core, output user_clock, output user_clock2, @@ -48,15 +57,14 @@ output [3:0] mprj_sel_o_user, output [31:0] mprj_adr_o_user, output [31:0] mprj_dat_o_user, - output [127:0] la_data_in_mprj, output user1_vcc_powergood, output user2_vcc_powergood, output user1_vdd_powergood, output user2_vdd_powergood ); - wire [74:0] mprj_logic1; - wire mprj2_logic1; + wire [458:0] mprj_logic1; + wire mprj2_logic1; wire mprj_vdd_logic1_h; wire mprj2_vdd_logic1_h; @@ -68,7 +76,7 @@ wire user1_vdd_powergood; wire user2_vdd_powergood; - sky130_fd_sc_hd__conb_1 mprj_logic_high [74:0] ( + sky130_fd_sc_hd__conb_1 mprj_logic_high [458:0] ( `ifdef USE_POWER_PINS .VPWR(vccd1), .VGND(vssd1), @@ -140,6 +148,30 @@ .A(mprj2_vdd_logic1_h) ); + // Buffering from the user side to the management side. + // NOTE: This is intended to be better protected, by a full + // chain of an lv-to-hv buffer followed by an hv-to-lv buffer. + // This serves as a placeholder until that configuration is + // checked and characterized. The function below forces the + // data input to the management core to be a solid logic 0 when + // the user project is powered down. + + sky130_fd_sc_hd__nor2b_4 user_to_mprj_in_buffers [127:0] ( +`ifdef USE_POWER_PINS + .VPWR(vccd), + .VGND(vssd), + .VPB(vccd), + .VNB(vssd), +`endif + .Y(la_data_in_mprj), + .A(mprj_logic1[457:330]), + .B_N(~la_data_out_core) + ); + + // The remaining circuitry guards against the management + // SoC dumping current into the user project area when + // the user project area is powered down. + sky130_fd_sc_hd__einvp_8 mprj_rstn_buf ( `ifdef USE_POWER_PINS .VPWR(vccd), @@ -250,11 +282,8 @@ .TE(mprj_logic1[73:42]) ); - /* The LA buffers are controlled from the user side, so */ - /* it is only necessary to make sure that the function */ - /* is inverting the OEB signal and using positive-sense */ - /* enable, so that the buffer is disabled on user-side */ - /* power-down of vccd1. */ + /* Project data out from the managment side to the user project */ + /* area when the user project is powered down. */ sky130_fd_sc_hd__einvp_8 la_buf [127:0] ( `ifdef USE_POWER_PINS @@ -263,11 +292,26 @@ .VPB(vccd), .VNB(vssd), `endif - .Z(la_data_in_mprj), - .A(~la_output_core), - .TE(~la_oen) + .Z(la_data_in_core), + .A(~la_data_out_mprj), + .TE(mprj_logic1[201:74]) ); + /* Project data out enable (bar) from the managment side to the */ + /* user project area when the user project is powered down. */ + + sky130_fd_sc_hd__einvp_8 user_to_mprj_oen_buffers [127:0] ( +`ifdef USE_POWER_PINS + .VPWR(vccd), + .VGND(vssd), + .VPB(vccd), + .VNB(vssd), +`endif + .Z(la_oen_core), + .A(~la_oen_mprj), + .TE(mprj_logic1[329:202]) + ); + /* The conb cell output is a resistive connection directly to */ /* the power supply, so when returning the user1_powergood */ /* signal, make sure that it is buffered properly. */ @@ -279,7 +323,7 @@ .VPB(vccd), .VNB(vssd), `endif - .A(mprj_logic1[74]), + .A(mprj_logic1[458]), .X(user1_vcc_powergood) ); @@ -290,7 +334,7 @@ .VPB(vccd), .VNB(vssd), `endif - .A(mprj2_logic1), + .A(mprj2_vdd_logic1), .X(user2_vcc_powergood) );