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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-009 / d4a2d6fbeb47e7956684a158adf406a173ef03e1 / . / openlane / user_proj_example / runs / user_proj_example / logs / synthesis / yosys.log
blob: 343398716bb71d2327ed53e437abc5c081c04d47 [file] [log] [blame]
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
1. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/defines.v
Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.
2. Executing Verilog-2005 frontend: /project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v
Parsing SystemVerilog input from `/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v' to AST representation.
Generating RTLIL representation for module `\user_proj_example'.
Generating RTLIL representation for module `\counter'.
Successfully finished Verilog frontend.
3. Generating Graphviz representation of design.
Writing dot description to `/project/openlane/user_proj_example/runs/user_proj_example/tmp/synthesis/hierarchy.dot'.
Dumping module user_proj_example to page 1.
4. Executing HIERARCHY pass (managing design hierarchy).
4.1. Analyzing design hierarchy..
Top module: \user_proj_example
Used module: \counter
Parameter \BITS = 32
4.2. Executing AST frontend in derive mode using pre-parsed AST for module `\counter'.
Parameter \BITS = 32
Generating RTLIL representation for module `$paramod\counter\BITS=32'.
4.3. Analyzing design hierarchy..
Top module: \user_proj_example
Used module: $paramod\counter\BITS=32
4.4. Analyzing design hierarchy..
Top module: \user_proj_example
Used module: $paramod\counter\BITS=32
Removing unused module `\counter'.
Removed 1 unused modules.
5. Executing SYNTH pass.
5.1. Executing HIERARCHY pass (managing design hierarchy).
5.1.1. Analyzing design hierarchy..
Top module: \user_proj_example
Used module: $paramod\counter\BITS=32
5.1.2. Analyzing design hierarchy..
Top module: \user_proj_example
Used module: $paramod\counter\BITS=32
Removed 0 unused modules.
5.2. Executing PROC pass (convert processes to netlists).
5.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
5.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:124$112 in module $paramod\counter\BITS=32.
Removed a total of 0 dead cases.
5.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 0 assignments to connections.
5.2.4. Executing PROC_INIT pass (extract init attributes).
5.2.5. Executing PROC_ARST pass (detect async resets in processes).
5.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$149'.
1/1: $0\count[31:31]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$148'.
1/1: $0\count[30:30]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$147'.
1/1: $0\count[29:29]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$146'.
1/1: $0\count[28:28]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$145'.
1/1: $0\count[27:27]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$144'.
1/1: $0\count[26:26]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$143'.
1/1: $0\count[25:25]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$142'.
1/1: $0\count[24:24]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$141'.
1/1: $0\count[23:23]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$140'.
1/1: $0\count[22:22]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$139'.
1/1: $0\count[21:21]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$138'.
1/1: $0\count[20:20]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$137'.
1/1: $0\count[19:19]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$136'.
1/1: $0\count[18:18]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$135'.
1/1: $0\count[17:17]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$134'.
1/1: $0\count[16:16]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$133'.
1/1: $0\count[15:15]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$132'.
1/1: $0\count[14:14]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$131'.
1/1: $0\count[13:13]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$130'.
1/1: $0\count[12:12]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$129'.
1/1: $0\count[11:11]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$128'.
1/1: $0\count[10:10]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$127'.
1/1: $0\count[9:9]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$126'.
1/1: $0\count[8:8]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$125'.
1/1: $0\count[7:7]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$124'.
1/1: $0\count[6:6]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$123'.
1/1: $0\count[5:5]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$122'.
1/1: $0\count[4:4]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$121'.
1/1: $0\count[3:3]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$120'.
1/1: $0\count[2:2]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$119'.
1/1: $0\count[1:1]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$118'.
1/1: $0\count[0:0]
Creating decoders for process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:124$112'.
1/6: $0\count[31:0] [31:24]
2/6: $0\count[31:0] [23:16]
3/6: $0\count[31:0] [15:8]
4/6: $0\count[31:0] [7:0]
5/6: $0\ready[0:0]
6/6: $0\rdata[31:0]
5.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).
5.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod\counter\BITS=32.\count [31]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$149'.
created $dff cell `$procdff$260' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [30]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$148'.
created $dff cell `$procdff$261' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [29]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$147'.
created $dff cell `$procdff$262' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [28]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$146'.
created $dff cell `$procdff$263' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [27]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$145'.
created $dff cell `$procdff$264' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [26]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$144'.
created $dff cell `$procdff$265' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [25]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$143'.
created $dff cell `$procdff$266' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [24]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$142'.
created $dff cell `$procdff$267' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [23]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$141'.
created $dff cell `$procdff$268' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [22]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$140'.
created $dff cell `$procdff$269' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [21]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$139'.
created $dff cell `$procdff$270' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [20]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$138'.
created $dff cell `$procdff$271' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [19]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$137'.
created $dff cell `$procdff$272' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [18]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$136'.
created $dff cell `$procdff$273' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [17]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$135'.
created $dff cell `$procdff$274' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [16]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$134'.
created $dff cell `$procdff$275' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [15]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$133'.
created $dff cell `$procdff$276' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [14]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$132'.
created $dff cell `$procdff$277' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [13]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$131'.
created $dff cell `$procdff$278' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [12]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$130'.
created $dff cell `$procdff$279' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [11]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$129'.
created $dff cell `$procdff$280' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [10]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$128'.
created $dff cell `$procdff$281' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [9]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$127'.
created $dff cell `$procdff$282' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [8]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$126'.
created $dff cell `$procdff$283' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [7]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$125'.
created $dff cell `$procdff$284' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [6]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$124'.
created $dff cell `$procdff$285' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [5]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$123'.
created $dff cell `$procdff$286' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [4]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$122'.
created $dff cell `$procdff$287' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [3]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$121'.
created $dff cell `$procdff$288' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [2]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$120'.
created $dff cell `$procdff$289' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [1]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$119'.
created $dff cell `$procdff$290' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count [0]' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$118'.
created $dff cell `$procdff$291' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\rdata' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:124$112'.
created $dff cell `$procdff$292' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\count' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:124$112'.
created $dff cell `$procdff$293' with positive edge clock.
Creating register for signal `$paramod\counter\BITS=32.\ready' using process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:124$112'.
created $dff cell `$procdff$294' with positive edge clock.
5.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$149'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$149'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$148'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$148'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$147'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$147'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$146'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$146'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$145'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$145'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$144'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$144'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$143'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$143'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$142'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$142'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$141'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$141'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$140'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$140'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$139'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$139'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$138'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$138'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$137'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$137'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$136'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$136'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$135'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$135'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$134'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$134'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$133'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$133'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$132'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$132'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$131'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$131'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$130'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$130'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$129'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$129'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$128'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$128'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$127'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$127'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$126'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$126'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$125'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$125'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$124'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$124'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$123'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$123'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$122'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$122'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$121'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$121'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$120'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$120'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$119'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$119'.
Found and cleaned up 1 empty switch in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$118'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:147$118'.
Found and cleaned up 7 empty switches in `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:124$112'.
Removing empty process `$paramod\counter\BITS=32.$proc$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:124$112'.
Cleaned up 39 empty switches.
5.3. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod\counter\BITS=32.
<suppressed ~1 debug messages>
5.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
<suppressed ~6 debug messages>
5.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
Removed 3 unused cells and 98 unused wires.
<suppressed ~4 debug messages>
5.6. Executing CHECK pass (checking for obvious problems).
checking module user_proj_example..
Warning: multiple conflicting drivers for user_proj_example.\counter.count [0]:
port Q[0] of cell $flatten\counter.$procdff$291 ($dff)
port Q[0] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [1]:
port Q[0] of cell $flatten\counter.$procdff$290 ($dff)
port Q[1] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [2]:
port Q[0] of cell $flatten\counter.$procdff$289 ($dff)
port Q[2] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [3]:
port Q[0] of cell $flatten\counter.$procdff$288 ($dff)
port Q[3] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [4]:
port Q[0] of cell $flatten\counter.$procdff$287 ($dff)
port Q[4] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [5]:
port Q[0] of cell $flatten\counter.$procdff$286 ($dff)
port Q[5] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [6]:
port Q[0] of cell $flatten\counter.$procdff$285 ($dff)
port Q[6] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [7]:
port Q[0] of cell $flatten\counter.$procdff$284 ($dff)
port Q[7] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [8]:
port Q[0] of cell $flatten\counter.$procdff$283 ($dff)
port Q[8] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [9]:
port Q[0] of cell $flatten\counter.$procdff$282 ($dff)
port Q[9] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [10]:
port Q[0] of cell $flatten\counter.$procdff$281 ($dff)
port Q[10] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [11]:
port Q[0] of cell $flatten\counter.$procdff$280 ($dff)
port Q[11] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [12]:
port Q[0] of cell $flatten\counter.$procdff$279 ($dff)
port Q[12] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [13]:
port Q[0] of cell $flatten\counter.$procdff$278 ($dff)
port Q[13] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [14]:
port Q[0] of cell $flatten\counter.$procdff$277 ($dff)
port Q[14] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [15]:
port Q[0] of cell $flatten\counter.$procdff$276 ($dff)
port Q[15] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [16]:
port Q[0] of cell $flatten\counter.$procdff$275 ($dff)
port Q[16] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [17]:
port Q[0] of cell $flatten\counter.$procdff$274 ($dff)
port Q[17] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [18]:
port Q[0] of cell $flatten\counter.$procdff$273 ($dff)
port Q[18] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [19]:
port Q[0] of cell $flatten\counter.$procdff$272 ($dff)
port Q[19] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [20]:
port Q[0] of cell $flatten\counter.$procdff$271 ($dff)
port Q[20] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [21]:
port Q[0] of cell $flatten\counter.$procdff$270 ($dff)
port Q[21] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [22]:
port Q[0] of cell $flatten\counter.$procdff$269 ($dff)
port Q[22] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [23]:
port Q[0] of cell $flatten\counter.$procdff$268 ($dff)
port Q[23] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [24]:
port Q[0] of cell $flatten\counter.$procdff$267 ($dff)
port Q[24] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [25]:
port Q[0] of cell $flatten\counter.$procdff$266 ($dff)
port Q[25] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [26]:
port Q[0] of cell $flatten\counter.$procdff$265 ($dff)
port Q[26] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [27]:
port Q[0] of cell $flatten\counter.$procdff$264 ($dff)
port Q[27] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [28]:
port Q[0] of cell $flatten\counter.$procdff$263 ($dff)
port Q[28] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [29]:
port Q[0] of cell $flatten\counter.$procdff$262 ($dff)
port Q[29] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [30]:
port Q[0] of cell $flatten\counter.$procdff$261 ($dff)
port Q[30] of cell $flatten\counter.$procdff$293 ($dff)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [31]:
port Q[0] of cell $flatten\counter.$procdff$260 ($dff)
port Q[31] of cell $flatten\counter.$procdff$293 ($dff)
found and reported 32 problems.
5.7. Executing OPT pass (performing simple optimizations).
5.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
5.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
5.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~44 debug messages>
5.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.
5.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
5.7.6. Executing OPT_DFF pass (perform DFF optimizations).
5.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
5.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
5.7.9. Finished OPT passes. (There is nothing left to do.)
5.8. Executing FSM pass (extract and optimize FSM).
5.8.1. Executing FSM_DETECT pass (finding FSMs in design).
5.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).
5.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).
5.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
5.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).
5.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
5.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
5.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
5.9. Executing OPT pass (performing simple optimizations).
5.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
5.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
5.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~44 debug messages>
5.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.
5.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
5.9.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\counter.$procdff$294 ($dff) from module user_proj_example (D = $flatten\counter.$procmux$250_Y, Q = \counter.ready, rval = 1'0).
Adding SRST signal on $flatten\counter.$procdff$293 ($dff) from module user_proj_example (D = { $flatten\counter.$procmux$218_Y $flatten\counter.$procmux$227_Y $flatten\counter.$procmux$236_Y $flatten\counter.$procmux$245_Y }, Q = \counter.count, rval = 0).
Adding EN signal on $flatten\counter.$procdff$292 ($dff) from module user_proj_example (D = \counter.count, Q = \counter.rdata).
Adding EN signal on $flatten\counter.$procdff$291 ($dff) from module user_proj_example (D = \la_data_in [32], Q = \counter.count [0]).
Adding EN signal on $flatten\counter.$procdff$290 ($dff) from module user_proj_example (D = \la_data_in [33], Q = \counter.count [1]).
Adding EN signal on $flatten\counter.$procdff$289 ($dff) from module user_proj_example (D = \la_data_in [34], Q = \counter.count [2]).
Adding EN signal on $flatten\counter.$procdff$288 ($dff) from module user_proj_example (D = \la_data_in [35], Q = \counter.count [3]).
Adding EN signal on $flatten\counter.$procdff$287 ($dff) from module user_proj_example (D = \la_data_in [36], Q = \counter.count [4]).
Adding EN signal on $flatten\counter.$procdff$286 ($dff) from module user_proj_example (D = \la_data_in [37], Q = \counter.count [5]).
Adding EN signal on $flatten\counter.$procdff$285 ($dff) from module user_proj_example (D = \la_data_in [38], Q = \counter.count [6]).
Adding EN signal on $flatten\counter.$procdff$284 ($dff) from module user_proj_example (D = \la_data_in [39], Q = \counter.count [7]).
Adding EN signal on $flatten\counter.$procdff$283 ($dff) from module user_proj_example (D = \la_data_in [40], Q = \counter.count [8]).
Adding EN signal on $flatten\counter.$procdff$282 ($dff) from module user_proj_example (D = \la_data_in [41], Q = \counter.count [9]).
Adding EN signal on $flatten\counter.$procdff$281 ($dff) from module user_proj_example (D = \la_data_in [42], Q = \counter.count [10]).
Adding EN signal on $flatten\counter.$procdff$280 ($dff) from module user_proj_example (D = \la_data_in [43], Q = \counter.count [11]).
Adding EN signal on $flatten\counter.$procdff$279 ($dff) from module user_proj_example (D = \la_data_in [44], Q = \counter.count [12]).
Adding EN signal on $flatten\counter.$procdff$278 ($dff) from module user_proj_example (D = \la_data_in [45], Q = \counter.count [13]).
Adding EN signal on $flatten\counter.$procdff$277 ($dff) from module user_proj_example (D = \la_data_in [46], Q = \counter.count [14]).
Adding EN signal on $flatten\counter.$procdff$276 ($dff) from module user_proj_example (D = \la_data_in [47], Q = \counter.count [15]).
Adding EN signal on $flatten\counter.$procdff$275 ($dff) from module user_proj_example (D = \la_data_in [48], Q = \counter.count [16]).
Adding EN signal on $flatten\counter.$procdff$274 ($dff) from module user_proj_example (D = \la_data_in [49], Q = \counter.count [17]).
Adding EN signal on $flatten\counter.$procdff$273 ($dff) from module user_proj_example (D = \la_data_in [50], Q = \counter.count [18]).
Adding EN signal on $flatten\counter.$procdff$272 ($dff) from module user_proj_example (D = \la_data_in [51], Q = \counter.count [19]).
Adding EN signal on $flatten\counter.$procdff$271 ($dff) from module user_proj_example (D = \la_data_in [52], Q = \counter.count [20]).
Adding EN signal on $flatten\counter.$procdff$270 ($dff) from module user_proj_example (D = \la_data_in [53], Q = \counter.count [21]).
Adding EN signal on $flatten\counter.$procdff$269 ($dff) from module user_proj_example (D = \la_data_in [54], Q = \counter.count [22]).
Adding EN signal on $flatten\counter.$procdff$268 ($dff) from module user_proj_example (D = \la_data_in [55], Q = \counter.count [23]).
Adding EN signal on $flatten\counter.$procdff$267 ($dff) from module user_proj_example (D = \la_data_in [56], Q = \counter.count [24]).
Adding EN signal on $flatten\counter.$procdff$266 ($dff) from module user_proj_example (D = \la_data_in [57], Q = \counter.count [25]).
Adding EN signal on $flatten\counter.$procdff$265 ($dff) from module user_proj_example (D = \la_data_in [58], Q = \counter.count [26]).
Adding EN signal on $flatten\counter.$procdff$264 ($dff) from module user_proj_example (D = \la_data_in [59], Q = \counter.count [27]).
Adding EN signal on $flatten\counter.$procdff$263 ($dff) from module user_proj_example (D = \la_data_in [60], Q = \counter.count [28]).
Adding EN signal on $flatten\counter.$procdff$262 ($dff) from module user_proj_example (D = \la_data_in [61], Q = \counter.count [29]).
Adding EN signal on $flatten\counter.$procdff$261 ($dff) from module user_proj_example (D = \la_data_in [62], Q = \counter.count [30]).
Adding EN signal on $flatten\counter.$procdff$260 ($dff) from module user_proj_example (D = \la_data_in [63], Q = \counter.count [31]).
5.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
Removed 39 unused cells and 36 unused wires.
<suppressed ~40 debug messages>
5.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
5.9.9. Rerunning OPT passes. (Maybe there is more to do..)
5.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~11 debug messages>
5.9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.
5.9.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
5.9.13. Executing OPT_DFF pass (perform DFF optimizations).
5.9.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
5.9.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
5.9.16. Finished OPT passes. (There is nothing left to do.)
5.10. Executing WREDUCE pass (reducing word size of cells).
Removed top 31 bits (of 32) from port B of cell user_proj_example.$flatten\counter.$add$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:131$115 ($add).
5.11. Executing PEEPOPT pass (run peephole optimizers).
5.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
5.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module user_proj_example:
creating $macc model for $flatten\counter.$add$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:131$115 ($add).
creating $alu model for $macc $flatten\counter.$add$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:131$115.
creating $alu cell for $flatten\counter.$add$/project/openlane/user_proj_example/../../verilog/rtl/user_proj_example.v:131$115: $auto$alumacc.cc:485:replace_alu$334
created 1 $alu and 0 $macc cells.
5.14. Executing SHARE pass (SAT-based resource sharing).
5.15. Executing OPT pass (performing simple optimizations).
5.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
5.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
5.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~11 debug messages>
5.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.
5.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
5.15.6. Executing OPT_DFF pass (perform DFF optimizations).
5.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
5.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
5.15.9. Finished OPT passes. (There is nothing left to do.)
5.16. Executing MEMORY pass.
5.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.
5.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
5.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
5.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
5.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
5.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).
5.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
5.18. Executing OPT pass (performing simple optimizations).
5.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
<suppressed ~4 debug messages>
5.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
5.18.3. Executing OPT_DFF pass (perform DFF optimizations).
5.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
Removed 0 unused cells and 2 unused wires.
<suppressed ~1 debug messages>
5.18.5. Finished fast OPT passes.
5.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
5.20. Executing OPT pass (performing simple optimizations).
5.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
5.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
5.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~10 debug messages>
5.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.
5.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
5.20.6. Executing OPT_SHARE pass.
5.20.7. Executing OPT_DFF pass (perform DFF optimizations).
5.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
5.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
5.20.10. Finished OPT passes. (There is nothing left to do.)
5.21. Executing TECHMAP pass (map to technology primitives).
5.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
5.21.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $logic_and.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $reduce_and.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu\WIDTH=32 for cells of type $lcu.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $or.
No more expansions possible.
<suppressed ~419 debug messages>
5.22. Executing OPT pass (performing simple optimizations).
5.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
<suppressed ~183 debug messages>
5.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.
5.22.3. Executing OPT_DFF pass (perform DFF optimizations).
5.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
Removed 36 unused cells and 116 unused wires.
<suppressed ~37 debug messages>
5.22.5. Finished fast OPT passes.
5.23. Executing ABC pass (technology mapping using ABC).
5.23.1. Extracting gate netlist of module `\user_proj_example' to `<abc-temp-dir>/input.blif'..
Extracted 287 gates and 397 wires to a netlist network with 110 inputs and 68 outputs.
5.23.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC:
ABC: + read_blif <abc-temp-dir>/input.blif
ABC: + read_library <abc-temp-dir>/stdcells.genlib
ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib".
ABC: + strash
ABC: + dretime
ABC: + map
ABC: + write_blif <abc-temp-dir>/output.blif
5.23.1.2. Re-integrating ABC results.
ABC RESULTS: AND cells: 6
ABC RESULTS: ANDNOT cells: 16
ABC RESULTS: MUX cells: 97
ABC RESULTS: NAND cells: 15
ABC RESULTS: NOR cells: 33
ABC RESULTS: NOT cells: 1
ABC RESULTS: OR cells: 51
ABC RESULTS: ORNOT cells: 1
ABC RESULTS: XNOR cells: 15
ABC RESULTS: XOR cells: 17
ABC RESULTS: internal signals: 219
ABC RESULTS: input signals: 110
ABC RESULTS: output signals: 68
Removing temp directory.
5.24. Executing OPT pass (performing simple optimizations).
5.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
<suppressed ~32 debug messages>
5.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
5.24.3. Executing OPT_DFF pass (perform DFF optimizations).
5.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
Removed 1 unused cells and 197 unused wires.
<suppressed ~6 debug messages>
5.24.5. Finished fast OPT passes.
5.25. Executing HIERARCHY pass (managing design hierarchy).
5.25.1. Analyzing design hierarchy..
Top module: \user_proj_example
5.25.2. Analyzing design hierarchy..
Top module: \user_proj_example
Removed 0 unused modules.
5.26. Printing statistics.
=== user_proj_example ===
Number of wires: 255
Number of wire bits: 1122
Number of public wires: 38
Number of public wire bits: 905
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 348
$_ANDNOT_ 16
$_AND_ 6
$_DFFE_PP_ 64
$_MUX_ 97
$_NAND_ 15
$_NOR_ 33
$_ORNOT_ 1
$_OR_ 51
$_SDFF_PP0_ 33
$_XNOR_ 15
$_XOR_ 17
5.27. Executing CHECK pass (checking for obvious problems).
checking module user_proj_example..
Warning: multiple conflicting drivers for user_proj_example.\counter.count [31]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$586 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$553 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [30]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$585 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$552 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [29]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$584 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$551 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [28]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$583 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$550 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [27]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$582 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$549 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [26]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$581 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$548 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [25]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$580 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$547 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [24]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$579 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$546 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [23]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$578 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$545 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [22]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$577 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$544 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [21]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$576 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$543 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [20]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$575 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$542 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [19]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$574 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$541 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [18]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$573 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$540 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [17]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$572 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$539 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [16]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$571 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$538 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [15]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$570 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$537 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [14]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$569 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$536 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [13]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$568 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$535 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [12]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$567 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$534 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [11]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$566 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$533 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [10]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$565 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$532 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [9]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$564 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$531 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [8]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$563 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$530 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [7]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$562 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$529 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [6]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$561 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$528 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [5]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$560 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$527 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [4]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$559 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$526 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [3]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$558 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$525 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [2]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$557 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$524 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [1]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$556 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$523 ($_SDFF_PP0_)
Warning: multiple conflicting drivers for user_proj_example.\counter.count [0]:
port Q[0] of cell $auto$simplemap.cc:442:simplemap_dffe$555 ($_DFFE_PP_)
port Q[0] of cell $auto$simplemap.cc:527:simplemap_adff_sdff$522 ($_SDFF_PP0_)
found and reported 32 problems.
6. Executing SHARE pass (SAT-based resource sharing).
7. Executing OPT pass (performing simple optimizations).
7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \user_proj_example..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \user_proj_example.
Performed a total of 0 changes.
7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\user_proj_example'.
Removed a total of 0 cells.
7.6. Executing OPT_DFF pass (perform DFF optimizations).
7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module user_proj_example.
7.9. Finished OPT passes. (There is nothing left to do.)
8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
Removed 0 unused cells and 11 unused wires.
<suppressed ~11 debug messages>
9. Printing statistics.
=== user_proj_example ===
Number of wires: 244
Number of wire bits: 863
Number of public wires: 27
Number of public wire bits: 646
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 348
$_ANDNOT_ 16
$_AND_ 6
$_DFFE_PP_ 64
$_MUX_ 97
$_NAND_ 15
$_NOR_ 33
$_ORNOT_ 1
$_OR_ 51
$_SDFF_PP0_ 33
$_XNOR_ 15
$_XOR_ 17
10. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
cell sky130_fd_sc_hd__dfxtp_4 (noninv, pins=3, area=23.77) is a direct match for cell type $_DFF_P_.
cell sky130_fd_sc_hd__dfrtp_4 (noninv, pins=4, area=28.78) is a direct match for cell type $_DFF_PN0_.
cell sky130_fd_sc_hd__dfstp_4 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFF_PN1_.
cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
final dff cell mappings:
unmapped dff cell: $_DFF_N_
\sky130_fd_sc_hd__dfxtp_4 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
unmapped dff cell: $_DFF_NN0_
unmapped dff cell: $_DFF_NN1_
unmapped dff cell: $_DFF_NP0_
unmapped dff cell: $_DFF_NP1_
\sky130_fd_sc_hd__dfrtp_4 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
\sky130_fd_sc_hd__dfstp_4 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
unmapped dff cell: $_DFF_PP0_
unmapped dff cell: $_DFF_PP1_
\sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
unmapped dff cell: $_DFFSR_NNP_
unmapped dff cell: $_DFFSR_NPN_
unmapped dff cell: $_DFFSR_NPP_
unmapped dff cell: $_DFFSR_PNN_
unmapped dff cell: $_DFFSR_PNP_
unmapped dff cell: $_DFFSR_PPN_
unmapped dff cell: $_DFFSR_PPP_
10.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\user_proj_example':
mapped 97 $_DFF_P_ cells to \sky130_fd_sc_hd__dfxtp_4 cells.
11. Printing statistics.
=== user_proj_example ===
Number of wires: 341
Number of wire bits: 960
Number of public wires: 27
Number of public wire bits: 646
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 445
$_ANDNOT_ 16
$_AND_ 6
$_MUX_ 194
$_NAND_ 15
$_NOR_ 33
$_ORNOT_ 1
$_OR_ 51
$_XNOR_ 15
$_XOR_ 17
sky130_fd_sc_hd__dfxtp_4 97
12. Executing ABC pass (technology mapping using ABC).
12.1. Extracting gate netlist of module `\user_proj_example' to `/tmp/yosys-abc-3d2WKh/input.blif'..
Extracted 348 gates and 523 wires to a netlist network with 174 inputs and 99 outputs.
12.1.1. Executing ABC.
Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-3d2WKh/abc.script 2>&1
ABC: ABC command line: "source /tmp/yosys-abc-3d2WKh/abc.script".
ABC:
ABC: + read_blif /tmp/yosys-abc-3d2WKh/input.blif
ABC: + read_lib -w /project/openlane/user_proj_example/runs/user_proj_example/tmp/trimmed.lib
ABC: Parsing finished successfully. Parsing time = 0.02 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/project/openlane/user_proj_example/runs/user_proj_example/tmp/trimmed.lib" has 43 cells (6 skipped: 6 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.03 sec
ABC: Memory = 1.82 MB. Time = 0.03 sec
ABC: + read_constr -v /project/openlane/user_proj_example/runs/user_proj_example/tmp/synthesis/yosys.sdc
ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8".
ABC: Setting output load to be 17.650000.
ABC: + read_constr /project/openlane/user_proj_example/runs/user_proj_example/tmp/synthesis/yosys.sdc
ABC: + fx
ABC: + mfs
ABC: + strash
ABC: + refactor
ABC: + balance
ABC: + rewrite
ABC: + refactor
ABC: + balance
ABC: + rewrite
ABC: + rewrite -z
ABC: + balance
ABC: + refactor -z
ABC: + rewrite -z
ABC: + balance
ABC: + retime -D -D 10000 -M 5
ABC: + scleanup
ABC: Error: The network is combinational.
ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000
ABC: + retime -D -D 10000
ABC: + buffer -N 5 -S 1000.0
ABC: Node 413 has dup fanin 5.
ABC: Node 413 has dup fanin 412.
ABC: Node 413 has dup fanin 5.
ABC: Node 413 has dup fanin 412.
ABC: Node 432 has dup fanin 13.
ABC: Node 432 has dup fanin 431.
ABC: Node 432 has dup fanin 13.
ABC: Node 432 has dup fanin 431.
ABC: Node 455 has dup fanin 21.
ABC: Node 455 has dup fanin 454.
ABC: Node 455 has dup fanin 21.
ABC: Node 455 has dup fanin 454.
ABC: Node 474 has dup fanin 29.
ABC: Node 474 has dup fanin 473.
ABC: Node 474 has dup fanin 29.
ABC: Node 474 has dup fanin 473.
ABC: Node 517 has dup fanin 45.
ABC: Node 517 has dup fanin 516.
ABC: Node 517 has dup fanin 45.
ABC: Node 517 has dup fanin 516.
ABC: Node 553 has dup fanin 303.
ABC: Node 553 has dup fanin 548.
ABC: Node 553 has dup fanin 303.
ABC: Node 553 has dup fanin 548.
ABC: Node 567 has dup fanin 389.
ABC: Node 567 has dup fanin 389.
ABC: Node 568 has dup fanin 388.
ABC: Node 568 has dup fanin 388.
ABC: Node 569 has dup fanin 390.
ABC: Node 569 has dup fanin 390.
ABC: Node 570 has dup fanin 387.
ABC: Node 570 has dup fanin 387.
ABC: Node 571 has dup fanin 384.
ABC: Node 571 has dup fanin 384.
ABC: Node 572 has dup fanin 383.
ABC: Node 572 has dup fanin 383.
ABC: Node 573 has dup fanin 385.
ABC: Node 573 has dup fanin 385.
ABC: Node 574 has dup fanin 382.
ABC: Node 574 has dup fanin 382.
ABC: Node 575 has dup fanin 379.
ABC: Node 575 has dup fanin 379.
ABC: Node 576 has dup fanin 378.
ABC: Node 576 has dup fanin 378.
ABC: Node 577 has dup fanin 380.
ABC: Node 577 has dup fanin 380.
ABC: Node 578 has dup fanin 377.
ABC: Node 578 has dup fanin 377.
ABC: Node 579 has dup fanin 374.
ABC: Node 579 has dup fanin 374.
ABC: Node 580 has dup fanin 373.
ABC: Node 580 has dup fanin 373.
ABC: Node 581 has dup fanin 375.
ABC: Node 581 has dup fanin 375.
ABC: Node 582 has dup fanin 372.
ABC: Node 582 has dup fanin 372.
ABC: Node 583 has dup fanin 368.
ABC: Node 583 has dup fanin 368.
ABC: Node 584 has dup fanin 367.
ABC: Node 584 has dup fanin 367.
ABC: Node 585 has dup fanin 369.
ABC: Node 585 has dup fanin 369.
ABC: Node 586 has dup fanin 366.
ABC: Node 586 has dup fanin 366.
ABC: Node 587 has dup fanin 363.
ABC: Node 587 has dup fanin 363.
ABC: Node 588 has dup fanin 362.
ABC: Node 588 has dup fanin 362.
ABC: Node 589 has dup fanin 364.
ABC: Node 589 has dup fanin 364.
ABC: Node 590 has dup fanin 361.
ABC: Node 590 has dup fanin 361.
ABC: Node 591 has dup fanin 358.
ABC: Node 591 has dup fanin 358.
ABC: Node 592 has dup fanin 357.
ABC: Node 592 has dup fanin 357.
ABC: Node 593 has dup fanin 359.
ABC: Node 593 has dup fanin 359.
ABC: Node 594 has dup fanin 356.
ABC: Node 594 has dup fanin 356.
ABC: Node 595 has dup fanin 353.
ABC: Node 595 has dup fanin 353.
ABC: Node 596 has dup fanin 352.
ABC: Node 596 has dup fanin 352.
ABC: Node 597 has dup fanin 354.
ABC: Node 597 has dup fanin 354.
ABC: Node 598 has dup fanin 351.
ABC: Node 598 has dup fanin 351.
ABC: Node 599 has dup fanin 566.
ABC: Node 599 has dup fanin 566.
ABC: Node 600 has dup fanin 566.
ABC: Node 600 has dup fanin 566.
ABC: Node 601 has dup fanin 566.
ABC: Node 601 has dup fanin 566.
ABC: Node 602 has dup fanin 566.
ABC: Node 602 has dup fanin 566.
ABC: Node 603 has dup fanin 566.
ABC: Node 603 has dup fanin 566.
ABC: Node 604 has dup fanin 566.
ABC: Node 604 has dup fanin 566.
ABC: Node 605 has dup fanin 566.
ABC: Node 605 has dup fanin 566.
ABC: Node 606 has dup fanin 566.
ABC: Node 606 has dup fanin 566.
ABC: Node 607 has dup fanin 566.
ABC: Node 607 has dup fanin 566.
ABC: Node 608 has dup fanin 566.
ABC: Node 608 has dup fanin 566.
ABC: Node 609 has dup fanin 566.
ABC: Node 609 has dup fanin 566.
ABC: Node 610 has dup fanin 566.
ABC: Node 610 has dup fanin 566.
ABC: Node 611 has dup fanin 566.
ABC: Node 611 has dup fanin 566.
ABC: Node 612 has dup fanin 566.
ABC: Node 612 has dup fanin 566.
ABC: Node 613 has dup fanin 566.
ABC: Node 613 has dup fanin 566.
ABC: Node 614 has dup fanin 566.
ABC: Node 614 has dup fanin 566.
ABC: Node 615 has dup fanin 566.
ABC: Node 615 has dup fanin 566.
ABC: Node 616 has dup fanin 566.
ABC: Node 616 has dup fanin 566.
ABC: Node 617 has dup fanin 566.
ABC: Node 617 has dup fanin 566.
ABC: Node 618 has dup fanin 566.
ABC: Node 618 has dup fanin 566.
ABC: Node 619 has dup fanin 566.
ABC: Node 619 has dup fanin 566.
ABC: Node 620 has dup fanin 566.
ABC: Node 620 has dup fanin 566.
ABC: Node 621 has dup fanin 566.
ABC: Node 621 has dup fanin 566.
ABC: Node 622 has dup fanin 566.
ABC: Node 622 has dup fanin 566.
ABC: Node 623 has dup fanin 566.
ABC: Node 623 has dup fanin 566.
ABC: Node 624 has dup fanin 566.
ABC: Node 624 has dup fanin 566.
ABC: Node 625 has dup fanin 566.
ABC: Node 625 has dup fanin 566.
ABC: Node 626 has dup fanin 566.
ABC: Node 626 has dup fanin 566.
ABC: Node 627 has dup fanin 566.
ABC: Node 627 has dup fanin 566.
ABC: Node 628 has dup fanin 566.
ABC: Node 628 has dup fanin 566.
ABC: Node 629 has dup fanin 566.
ABC: Node 629 has dup fanin 566.
ABC: Node 630 has dup fanin 566.
ABC: Node 630 has dup fanin 566.
ABC: + upsize -D 10000
ABC: Current delay (3789.48 ps) does not exceed the target delay (10000.00 ps). Upsizing is not performed.
ABC: + dnsize -D 10000
ABC: + stime -p
ABC: WireLoad = "none" Gates = 404 ( 33.9 %) Cap = 10.3 ff ( 0.0 %) Area = 4299.12 (100.0 %) Delay = 3976.25 ps ( 5.9 %)
ABC: Path 0 -- 98 : 0 1 pi A = 0.00 Df = 3.4 -2.5 ps S = 14.9 ps Cin = 0.0 ff Cout = 2.6 ff Cmax = 0.0 ff G = 0
ABC: Path 1 -- 280 : 2 1 sky130_fd_sc_hd__and2_4 A = 8.76 Df = 128.0 -12.8 ps S = 29.0 ps Cin = 2.4 ff Cout = 1.8 ff Cmax = 539.3 ff G = 72
ABC: Path 2 -- 281 : 1 5 sky130_fd_sc_hd__buf_2 A = 5.00 Df = 248.8 -25.7 ps S = 55.5 ps Cin = 1.7 ff Cout = 9.0 ff Cmax = 315.9 ff G = 500
ABC: Path 3 -- 282 : 1 5 sky130_fd_sc_hd__buf_2 A = 5.00 Df = 416.2 -3.1 ps S = 159.6 ps Cin = 1.7 ff Cout = 31.5 ff Cmax = 315.9 ff G = 1709
ABC: Path 4 -- 348 : 1 5 sky130_fd_sc_hd__buf_2 A = 5.00 Df = 693.4 -75.2 ps S = 230.7 ps Cin = 1.7 ff Cout = 46.4 ff Cmax = 315.9 ff G = 2515
ABC: Path 5 -- 360 : 2 3 sky130_fd_sc_hd__nor2_4 A = 11.26 Df = 752.5 -9.7 ps S = 105.5 ps Cin = 8.7 ff Cout = 11.8 ff Cmax = 251.8 ff G = 127
ABC: Path 6 -- 361 : 4 1 sky130_fd_sc_hd__or4_4 A = 11.26 Df =1152.7 -287.6 ps S = 77.7 ps Cin = 2.4 ff Cout = 2.5 ff Cmax = 534.7 ff G = 98
ABC: Path 7 -- 377 : 4 1 sky130_fd_sc_hd__or4_4 A = 11.26 Df =1677.8 -712.3 ps S = 77.6 ps Cin = 2.4 ff Cout = 2.5 ff Cmax = 534.7 ff G = 99
ABC: Path 8 -- 378 : 2 4 sky130_fd_sc_hd__or2_4 A = 8.76 Df =1922.5 -849.6 ps S = 52.9 ps Cin = 2.4 ff Cout = 9.4 ff Cmax = 514.5 ff G = 370
ABC: Path 9 -- 379 : 4 4 sky130_fd_sc_hd__or4_4 A = 11.26 Df =2371.1-1164.4 ps S = 106.3 ps Cin = 2.4 ff Cout = 16.8 ff Cmax = 534.7 ff G = 657
ABC: Path 10 -- 380 : 4 3 sky130_fd_sc_hd__or4_4 A = 11.26 Df =2828.4-1485.7 ps S = 102.2 ps Cin = 2.4 ff Cout = 14.3 ff Cmax = 534.7 ff G = 561
ABC: Path 11 -- 381 : 3 2 sky130_fd_sc_hd__or3_4 A = 11.26 Df =3188.2-1717.5 ps S = 77.8 ps Cin = 2.4 ff Cout = 11.8 ff Cmax = 531.9 ff G = 476
ABC: Path 12 -- 383 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df =3453.2-1845.0 ps S = 72.5 ps Cin = 2.4 ff Cout = 19.3 ff Cmax = 514.5 ff G = 764
ABC: Path 13 -- 676 : 4 1 sky130_fd_sc_hd__a211o_4 A = 17.52 Df =3778.0 -157.3 ps S = 44.5 ps Cin = 4.6 ff Cout = 2.5 ff Cmax = 559.4 ff G = 52
ABC: Path 14 -- 677 : 3 1 sky130_fd_sc_hd__and3_4 A = 11.26 Df =3976.3 -149.6 ps S = 80.5 ps Cin = 2.4 ff Cout = 17.6 ff Cmax = 532.8 ff G = 729
ABC: Start-point = pi97 (\wbs_cyc_i). End-point = po98 ($auto$rtlil.cc:2290:MuxGate$1713).
ABC: + print_stats -m
ABC: netlist : i/o = 174/ 99 lat = 0 nd = 404 edge = 954 area =4298.70 delay =16.00 lev = 16
ABC: + write_blif /tmp/yosys-abc-3d2WKh/output.blif
12.1.2. Re-integrating ABC results.
ABC RESULTS: sky130_fd_sc_hd__a211o_4 cells: 14
ABC RESULTS: sky130_fd_sc_hd__a21bo_4 cells: 1
ABC RESULTS: sky130_fd_sc_hd__a21o_4 cells: 7
ABC RESULTS: sky130_fd_sc_hd__a2bb2o_4 cells: 70
ABC RESULTS: sky130_fd_sc_hd__a32o_4 cells: 8
ABC RESULTS: sky130_fd_sc_hd__and2_4 cells: 13
ABC RESULTS: sky130_fd_sc_hd__and3_4 cells: 16
ABC RESULTS: sky130_fd_sc_hd__buf_2 cells: 42
ABC RESULTS: sky130_fd_sc_hd__inv_2 cells: 95
ABC RESULTS: sky130_fd_sc_hd__nand2_4 cells: 5
ABC RESULTS: sky130_fd_sc_hd__nor2_4 cells: 51
ABC RESULTS: sky130_fd_sc_hd__o21ai_4 cells: 7
ABC RESULTS: sky130_fd_sc_hd__o22a_4 cells: 3
ABC RESULTS: sky130_fd_sc_hd__or2_4 cells: 43
ABC RESULTS: sky130_fd_sc_hd__or3_4 cells: 4
ABC RESULTS: sky130_fd_sc_hd__or4_4 cells: 25
ABC RESULTS: internal signals: 250
ABC RESULTS: input signals: 174
ABC RESULTS: output signals: 99
Removing temp directory.
13. Executing SETUNDEF pass (replace undef values with defined constants).
14. Executing HILOMAP pass (mapping to constant drivers).
15. Executing SPLITNETS pass (splitting up multi-bit signals).
16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_proj_example..
Removed 0 unused cells and 626 unused wires.
<suppressed ~34 debug messages>
17. Executing INSBUF pass (insert buffer cells for connected wires).
Added user_proj_example.$auto$insbuf.cc:79:execute$2325: \io_oeb [36] -> \io_oeb [0]
Added user_proj_example.$auto$insbuf.cc:79:execute$2326: \io_oeb [36] -> \io_oeb [1]
Added user_proj_example.$auto$insbuf.cc:79:execute$2327: \io_oeb [36] -> \io_oeb [2]
Added user_proj_example.$auto$insbuf.cc:79:execute$2328: \io_oeb [36] -> \io_oeb [3]
Added user_proj_example.$auto$insbuf.cc:79:execute$2329: \io_oeb [36] -> \io_oeb [4]
Added user_proj_example.$auto$insbuf.cc:79:execute$2330: \io_oeb [36] -> \io_oeb [5]
Added user_proj_example.$auto$insbuf.cc:79:execute$2331: \io_oeb [36] -> \io_oeb [6]
Added user_proj_example.$auto$insbuf.cc:79:execute$2332: \io_oeb [36] -> \io_oeb [7]
Added user_proj_example.$auto$insbuf.cc:79:execute$2333: \io_oeb [36] -> \io_oeb [8]
Added user_proj_example.$auto$insbuf.cc:79:execute$2334: \io_oeb [36] -> \io_oeb [9]
Added user_proj_example.$auto$insbuf.cc:79:execute$2335: \io_oeb [36] -> \io_oeb [10]
Added user_proj_example.$auto$insbuf.cc:79:execute$2336: \io_oeb [36] -> \io_oeb [11]
Added user_proj_example.$auto$insbuf.cc:79:execute$2337: \io_oeb [36] -> \io_oeb [12]
Added user_proj_example.$auto$insbuf.cc:79:execute$2338: \io_oeb [36] -> \io_oeb [13]
Added user_proj_example.$auto$insbuf.cc:79:execute$2339: \io_oeb [36] -> \io_oeb [14]
Added user_proj_example.$auto$insbuf.cc:79:execute$2340: \io_oeb [36] -> \io_oeb [15]
Added user_proj_example.$auto$insbuf.cc:79:execute$2341: \io_oeb [36] -> \io_oeb [16]
Added user_proj_example.$auto$insbuf.cc:79:execute$2342: \io_oeb [36] -> \io_oeb [17]
Added user_proj_example.$auto$insbuf.cc:79:execute$2343: \io_oeb [36] -> \io_oeb [18]
Added user_proj_example.$auto$insbuf.cc:79:execute$2344: \io_oeb [36] -> \io_oeb [19]
Added user_proj_example.$auto$insbuf.cc:79:execute$2345: \io_oeb [36] -> \io_oeb [20]
Added user_proj_example.$auto$insbuf.cc:79:execute$2346: \io_oeb [36] -> \io_oeb [21]
Added user_proj_example.$auto$insbuf.cc:79:execute$2347: \io_oeb [36] -> \io_oeb [22]
Added user_proj_example.$auto$insbuf.cc:79:execute$2348: \io_oeb [36] -> \io_oeb [23]
Added user_proj_example.$auto$insbuf.cc:79:execute$2349: \io_oeb [36] -> \io_oeb [24]
Added user_proj_example.$auto$insbuf.cc:79:execute$2350: \io_oeb [36] -> \io_oeb [25]
Added user_proj_example.$auto$insbuf.cc:79:execute$2351: \io_oeb [36] -> \io_oeb [26]
Added user_proj_example.$auto$insbuf.cc:79:execute$2352: \io_oeb [36] -> \io_oeb [27]
Added user_proj_example.$auto$insbuf.cc:79:execute$2353: \io_oeb [36] -> \io_oeb [28]
Added user_proj_example.$auto$insbuf.cc:79:execute$2354: \io_oeb [36] -> \io_oeb [29]
Added user_proj_example.$auto$insbuf.cc:79:execute$2355: \io_oeb [36] -> \io_oeb [30]
Added user_proj_example.$auto$insbuf.cc:79:execute$2356: \io_oeb [36] -> \io_oeb [31]
Added user_proj_example.$auto$insbuf.cc:79:execute$2357: \io_oeb [36] -> \io_oeb [32]
Added user_proj_example.$auto$insbuf.cc:79:execute$2358: \io_oeb [36] -> \io_oeb [33]
Added user_proj_example.$auto$insbuf.cc:79:execute$2359: \io_oeb [36] -> \io_oeb [34]
Added user_proj_example.$auto$insbuf.cc:79:execute$2360: \io_oeb [36] -> \io_oeb [35]
Added user_proj_example.$auto$insbuf.cc:79:execute$2361: \io_out [0] -> \la_data_out [0]
Added user_proj_example.$auto$insbuf.cc:79:execute$2362: \io_out [1] -> \la_data_out [1]
Added user_proj_example.$auto$insbuf.cc:79:execute$2363: \io_out [2] -> \la_data_out [2]
Added user_proj_example.$auto$insbuf.cc:79:execute$2364: \io_out [3] -> \la_data_out [3]
Added user_proj_example.$auto$insbuf.cc:79:execute$2365: \io_out [4] -> \la_data_out [4]
Added user_proj_example.$auto$insbuf.cc:79:execute$2366: \io_out [5] -> \la_data_out [5]
Added user_proj_example.$auto$insbuf.cc:79:execute$2367: \io_out [6] -> \la_data_out [6]
Added user_proj_example.$auto$insbuf.cc:79:execute$2368: \io_out [7] -> \la_data_out [7]
Added user_proj_example.$auto$insbuf.cc:79:execute$2369: \io_out [8] -> \la_data_out [8]
Added user_proj_example.$auto$insbuf.cc:79:execute$2370: \io_out [9] -> \la_data_out [9]
Added user_proj_example.$auto$insbuf.cc:79:execute$2371: \io_out [10] -> \la_data_out [10]
Added user_proj_example.$auto$insbuf.cc:79:execute$2372: \io_out [11] -> \la_data_out [11]
Added user_proj_example.$auto$insbuf.cc:79:execute$2373: \io_out [12] -> \la_data_out [12]
Added user_proj_example.$auto$insbuf.cc:79:execute$2374: \io_out [13] -> \la_data_out [13]
Added user_proj_example.$auto$insbuf.cc:79:execute$2375: \io_out [14] -> \la_data_out [14]
Added user_proj_example.$auto$insbuf.cc:79:execute$2376: \io_out [15] -> \la_data_out [15]
Added user_proj_example.$auto$insbuf.cc:79:execute$2377: \io_out [16] -> \la_data_out [16]
Added user_proj_example.$auto$insbuf.cc:79:execute$2378: \io_out [17] -> \la_data_out [17]
Added user_proj_example.$auto$insbuf.cc:79:execute$2379: \io_out [18] -> \la_data_out [18]
Added user_proj_example.$auto$insbuf.cc:79:execute$2380: \io_out [19] -> \la_data_out [19]
Added user_proj_example.$auto$insbuf.cc:79:execute$2381: \io_out [20] -> \la_data_out [20]
Added user_proj_example.$auto$insbuf.cc:79:execute$2382: \io_out [21] -> \la_data_out [21]
Added user_proj_example.$auto$insbuf.cc:79:execute$2383: \io_out [22] -> \la_data_out [22]
Added user_proj_example.$auto$insbuf.cc:79:execute$2384: \io_out [23] -> \la_data_out [23]
Added user_proj_example.$auto$insbuf.cc:79:execute$2385: \io_out [24] -> \la_data_out [24]
Added user_proj_example.$auto$insbuf.cc:79:execute$2386: \io_out [25] -> \la_data_out [25]
Added user_proj_example.$auto$insbuf.cc:79:execute$2387: \io_out [26] -> \la_data_out [26]
Added user_proj_example.$auto$insbuf.cc:79:execute$2388: \io_out [27] -> \la_data_out [27]
Added user_proj_example.$auto$insbuf.cc:79:execute$2389: \io_out [28] -> \la_data_out [28]
Added user_proj_example.$auto$insbuf.cc:79:execute$2390: \io_out [29] -> \la_data_out [29]
Added user_proj_example.$auto$insbuf.cc:79:execute$2391: \io_out [30] -> \la_data_out [30]
Added user_proj_example.$auto$insbuf.cc:79:execute$2392: \io_out [31] -> \la_data_out [31]
18. Executing CHECK pass (checking for obvious problems).
checking module user_proj_example..
Warning: Wire user_proj_example.\wbs_dat_o [31] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [30] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [29] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [28] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [27] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [26] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [25] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [24] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [23] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [22] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [21] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [20] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [19] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [18] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [17] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [16] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [15] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [14] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [13] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [12] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [11] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [10] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [9] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [8] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [7] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [6] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [5] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [4] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [3] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [2] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [1] is used but has no driver.
Warning: Wire user_proj_example.\wbs_dat_o [0] is used but has no driver.
Warning: Wire user_proj_example.\wbs_ack_o is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [127] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [126] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [125] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [124] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [123] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [122] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [121] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [120] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [119] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [118] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [117] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [116] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [115] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [114] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [113] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [112] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [111] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [110] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [109] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [108] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [107] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [106] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [105] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [104] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [103] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [102] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [101] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [100] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [99] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [98] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [97] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [96] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [95] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [94] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [93] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [92] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [91] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [90] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [89] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [88] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [87] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [86] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [85] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [84] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [83] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [82] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [81] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [80] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [79] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [78] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [77] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [76] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [75] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [74] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [73] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [72] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [71] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [70] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [69] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [68] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [67] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [66] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [65] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [64] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [63] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [62] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [61] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [60] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [59] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [58] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [57] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [56] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [55] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [54] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [53] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [52] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [51] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [50] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [49] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [48] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [47] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [46] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [45] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [44] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [43] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [42] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [41] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [40] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [39] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [38] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [37] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [36] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [35] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [34] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [33] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [32] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [31] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [30] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [29] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [28] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [27] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [26] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [25] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [24] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [23] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [22] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [21] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [20] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [19] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [18] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [17] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [16] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [15] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [14] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [13] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [12] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [11] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [10] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [9] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [8] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [7] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [6] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [5] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [4] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [3] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [2] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [1] is used but has no driver.
Warning: Wire user_proj_example.\la_data_out [0] is used but has no driver.
Warning: Wire user_proj_example.\io_out [37] is used but has no driver.
Warning: Wire user_proj_example.\io_out [36] is used but has no driver.
Warning: Wire user_proj_example.\io_out [35] is used but has no driver.
Warning: Wire user_proj_example.\io_out [34] is used but has no driver.
Warning: Wire user_proj_example.\io_out [33] is used but has no driver.
Warning: Wire user_proj_example.\io_out [32] is used but has no driver.
Warning: Wire user_proj_example.\io_out [31] is used but has no driver.
Warning: Wire user_proj_example.\io_out [30] is used but has no driver.
Warning: Wire user_proj_example.\io_out [29] is used but has no driver.
Warning: Wire user_proj_example.\io_out [28] is used but has no driver.
Warning: Wire user_proj_example.\io_out [27] is used but has no driver.
Warning: Wire user_proj_example.\io_out [26] is used but has no driver.
Warning: Wire user_proj_example.\io_out [25] is used but has no driver.
Warning: Wire user_proj_example.\io_out [24] is used but has no driver.
Warning: Wire user_proj_example.\io_out [23] is used but has no driver.
Warning: Wire user_proj_example.\io_out [22] is used but has no driver.
Warning: Wire user_proj_example.\io_out [21] is used but has no driver.
Warning: Wire user_proj_example.\io_out [20] is used but has no driver.
Warning: Wire user_proj_example.\io_out [19] is used but has no driver.
Warning: Wire user_proj_example.\io_out [18] is used but has no driver.
Warning: Wire user_proj_example.\io_out [17] is used but has no driver.
Warning: Wire user_proj_example.\io_out [16] is used but has no driver.
Warning: Wire user_proj_example.\io_out [15] is used but has no driver.
Warning: Wire user_proj_example.\io_out [14] is used but has no driver.
Warning: Wire user_proj_example.\io_out [13] is used but has no driver.
Warning: Wire user_proj_example.\io_out [12] is used but has no driver.
Warning: Wire user_proj_example.\io_out [11] is used but has no driver.
Warning: Wire user_proj_example.\io_out [10] is used but has no driver.
Warning: Wire user_proj_example.\io_out [9] is used but has no driver.
Warning: Wire user_proj_example.\io_out [8] is used but has no driver.
Warning: Wire user_proj_example.\io_out [7] is used but has no driver.
Warning: Wire user_proj_example.\io_out [6] is used but has no driver.
Warning: Wire user_proj_example.\io_out [5] is used but has no driver.
Warning: Wire user_proj_example.\io_out [4] is used but has no driver.
Warning: Wire user_proj_example.\io_out [3] is used but has no driver.
Warning: Wire user_proj_example.\io_out [2] is used but has no driver.
Warning: Wire user_proj_example.\io_out [1] is used but has no driver.
Warning: Wire user_proj_example.\io_out [0] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [37] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [36] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [35] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [34] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [33] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [32] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [31] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [30] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [29] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [28] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [27] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [26] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [25] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [24] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [23] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [22] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [21] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [20] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [19] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [18] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [17] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [16] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [15] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [14] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [13] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [12] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [11] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [10] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [9] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [8] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [7] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [6] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [5] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [4] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [3] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [2] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [1] is used but has no driver.
Warning: Wire user_proj_example.\io_oeb [0] is used but has no driver.
found and reported 237 problems.
19. Printing statistics.
=== user_proj_example ===
Number of wires: 427
Number of wire bits: 1015
Number of public wires: 25
Number of public wire bits: 613
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 672
sky130_fd_sc_hd__a211o_4 14
sky130_fd_sc_hd__a21bo_4 1
sky130_fd_sc_hd__a21o_4 7
sky130_fd_sc_hd__a2bb2o_4 70
sky130_fd_sc_hd__a32o_4 8
sky130_fd_sc_hd__and2_4 13
sky130_fd_sc_hd__and3_4 16
sky130_fd_sc_hd__buf_2 110
sky130_fd_sc_hd__conb_1 103
sky130_fd_sc_hd__dfxtp_4 97
sky130_fd_sc_hd__inv_2 95
sky130_fd_sc_hd__nand2_4 5
sky130_fd_sc_hd__nor2_4 51
sky130_fd_sc_hd__o21ai_4 7
sky130_fd_sc_hd__o22a_4 3
sky130_fd_sc_hd__or2_4 43
sky130_fd_sc_hd__or3_4 4
sky130_fd_sc_hd__or4_4 25
Chip area for module '\user_proj_example': 7332.032000
20. Executing Verilog backend.
Dumping module `\user_proj_example'.
Warnings: 301 unique messages, 301 total
End of script. Logfile hash: c81f427594, CPU: user 0.82s system 0.02s, MEM: 44.71 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 42% 2x abc (0 sec), 20% 4x stat (0 sec), ...