openlane/mgmt_core/runs/mgmt_core/logs/cts/cts.log

OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Error: cannot open '/.openroad'.
Notice 0: Reading LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 440 library cells
Notice 0: Finished LEF file:  /project/openlane/mgmt_core/runs/mgmt_core/tmp/merged_unpadded.lef
Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: 
Reading DEF file: /project/openlane/mgmt_core/runs/mgmt_core/results/placement/mgmt_core.placement.def
Notice 0: Design: mgmt_core
Notice 0:     Created 796 pins.
Notice 0:     Created 54642 components and 299480 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 36737 nets and 115154 connections.
Notice 0: Finished DEF file: /project/openlane/mgmt_core/runs/mgmt_core/results/placement/mgmt_core.placement.def
[INFO]: Setting output delay to: 10.0
[INFO]: Setting input delay to: 10.0
[INFO]: Setting load to: 0.01765
[INFO]: Configuring cts characterization...
[INFO]: Performing clock tree synthesis...
[INFO]: Looking for the following net(s): clock
 *****************
 * TritonCTS 2.0 *
 *****************
 *****************************
 *  Create characterization  *
 *****************************
Number of created patterns = 50000.
Number of created patterns = 100000.
Number of created patterns = 150000.
Number of created patterns = 200000.
Number of created patterns = 250000.
Number of created patterns = 300000.
Number of created patterns = 313632.
 Compiling LUT
    Min. len    Max. len    Min. cap    Max. cap   Min. slew   Max. slew
           2           8           1          39           1         318
    [WARNING] 6336 wires are pure wire and no slew degration.
    TritonCTS forced slew degradation on these wires.
    Num wire segments: 313632
    Num keys in characterization LUT: 2039
    Actual min input cap: 2
 **********************
 *  Find clock roots  *
 **********************
 Running TritonCTS with user-specified clock roots: clock
 ************************
 *  Populate TritonCTS  *
 ************************
 Initializing clock nets
 Looking for clock nets in the design
 Net "clock" found
 Initializing clock net for : "clock"
 Clock net "clock" has 3 sinks
 TritonCTS found 1 clock nets.
 ****************************
 *  Check characterization  *
 ****************************
    The chacterization used 4 buffer(s) types. All of them are in the loaded DB.
 ***********************
 *  Build clock trees  *
 ***********************
 Generating H-Tree topology for net clock...
    Tot. number of sinks: 3
    Number of static layers: 0
 Wire segment unit: 13000 dbu (13 um)
 Original sink region: [(1598240, 50505), (1777035, 59470)]
 Normalized sink region: [(122.942, 3.885), (136.695, 4.57462)]
    Width:  13.7535
    Height: 0.689615
 [WARNING] Creating fake entries in the LUT.
 Level 1
    Direction: Horizontal
    # sinks per sub-region: 2
    Sub-region size: 6.87673 X 0.689615
    Segment length (rounded): 1
    Key: 313864 outSlew: 11 load: 1 length: 1 isBuffered: 1
 Stop criterion found. Max number of sinks is (15)
 Building clock sub nets...
 Number of sinks covered: 3
 Clock topology of net "clock" done.
 ****************
 * Post CTS opt *
 ****************
 Avg. source sink dist: 66732.3 dbu.
 Num outlier sinks: 0
 ********************
 * Write data to DB *
 ********************
 Writing clock net "clock" to DB
    Created 3 clock buffers.
    Minimum number of buffers in the clock path: 2.
    Maximum number of buffers in the clock path: 2.
    Created 3 clock nets.
    Fanout distribution for the current clock = 1:1, 2:1.
    Max level of the clock tree: 1.
 ... End of TritonCTS execution.
[INFO]: Legalizing...
Design Stats
--------------------------------
total instances         54645
multi row instances         0
fixed instances         18288
nets                    36742
design area          1768316.0 u^2
fixed area            29400.5 u^2
movable area         408465.5 u^2
utilization                23 %
utilization padded         23 %
rows                      304
row height                2.7 u

Placement Analysis
--------------------------------
total displacement       55.6 u
average displacement      0.0 u
max displacement         30.0 u
original HPWL        2860521.0 u
legalized HPWL       2860513.8 u
delta HPWL                 -0 %