Google Git
Sign in
foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-009 / d4a2d6fbeb47e7956684a158adf406a173ef03e1 / . / openlane / gpio_control_block / runs / gpio_control_block / logs / synthesis / yosys.log
blob: c7a9522dcdcf228119a008d4e2707be7da79a3ac [file] [log] [blame]
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
1. Executing Liberty frontend.
Imported 428 cell types from liberty file.
2. Executing Verilog-2005 frontend: /project/openlane/gpio_control_block/../../verilog/rtl/defines.v
Parsing SystemVerilog input from `/project/openlane/gpio_control_block/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.
3. Executing Verilog-2005 frontend: /project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v
Parsing SystemVerilog input from `/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:199)
Generating RTLIL representation for module `\gpio_control_block'.
Successfully finished Verilog frontend.
4. Generating Graphviz representation of design.
Writing dot description to `/project/openlane/gpio_control_block/runs/gpio_control_block/tmp/synthesis/hierarchy.dot'.
Dumping module gpio_control_block to page 1.
5. Executing HIERARCHY pass (managing design hierarchy).
5.1. Analyzing design hierarchy..
Top module: \gpio_control_block
5.2. Analyzing design hierarchy..
Top module: \gpio_control_block
Removed 0 unused modules.
6. Executing SYNTH pass.
6.1. Executing HIERARCHY pass (managing design hierarchy).
6.1.1. Analyzing design hierarchy..
Top module: \gpio_control_block
6.1.2. Analyzing design hierarchy..
Top module: \gpio_control_block
Removed 0 unused modules.
6.2. Executing PROC pass (convert processes to netlists).
6.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
6.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:151$8 in module gpio_control_block.
Marked 1 switch rules as full_case in process $proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:141$6 in module gpio_control_block.
Removed a total of 0 dead cases.
6.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 12 redundant assignments.
Promoted 0 assignments to connections.
6.2.4. Executing PROC_INIT pass (extract init attributes).
6.2.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \int_reset in `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:151$8'.
Found async reset \int_reset in `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:141$6'.
6.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:151$8'.
1/11: $0\gpio_dm[2:0]
2/11: $0\gpio_vtrip_sel[0:0]
3/11: $0\gpio_slow_sel[0:0]
4/11: $0\gpio_ana_pol[0:0]
5/11: $0\gpio_ana_sel[0:0]
6/11: $0\gpio_ana_en[0:0]
7/11: $0\gpio_ib_mode_sel[0:0]
8/11: $0\gpio_inenb[0:0]
9/11: $0\gpio_holdover[0:0]
10/11: $0\gpio_outenb[0:0]
11/11: $0\mgmt_ena[0:0]
Creating decoders for process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:141$6'.
1/1: $0\shift_register[12:0]
6.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).
6.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\gpio_control_block.\mgmt_ena' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:151$8'.
created $adff cell `$procdff$24' with positive edge clock and positive level reset.
Creating register for signal `\gpio_control_block.\gpio_holdover' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:151$8'.
created $adff cell `$procdff$25' with positive edge clock and positive level reset.
Creating register for signal `\gpio_control_block.\gpio_slow_sel' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:151$8'.
created $adff cell `$procdff$26' with positive edge clock and positive level reset.
Creating register for signal `\gpio_control_block.\gpio_vtrip_sel' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:151$8'.
created $adff cell `$procdff$27' with positive edge clock and positive level reset.
Creating register for signal `\gpio_control_block.\gpio_inenb' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:151$8'.
created $adff cell `$procdff$28' with positive edge clock and positive level reset.
Creating register for signal `\gpio_control_block.\gpio_ib_mode_sel' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:151$8'.
created $adff cell `$procdff$29' with positive edge clock and positive level reset.
Creating register for signal `\gpio_control_block.\gpio_outenb' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:151$8'.
created $adff cell `$procdff$30' with positive edge clock and positive level reset.
Creating register for signal `\gpio_control_block.\gpio_dm' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:151$8'.
created $adff cell `$procdff$31' with positive edge clock and positive level reset.
Creating register for signal `\gpio_control_block.\gpio_ana_en' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:151$8'.
created $adff cell `$procdff$32' with positive edge clock and positive level reset.
Creating register for signal `\gpio_control_block.\gpio_ana_sel' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:151$8'.
created $adff cell `$procdff$33' with positive edge clock and positive level reset.
Creating register for signal `\gpio_control_block.\gpio_ana_pol' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:151$8'.
created $adff cell `$procdff$34' with positive edge clock and positive level reset.
Creating register for signal `\gpio_control_block.\shift_register' using process `\gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:141$6'.
created $adff cell `$procdff$35' with positive edge clock and positive level reset.
6.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:151$8'.
Removing empty process `gpio_control_block.$proc$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:141$6'.
Cleaned up 0 empty switches.
6.3. Executing FLATTEN pass (flatten design).
6.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.
<suppressed ~6 debug messages>
6.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
Removed 1 unused cells and 23 unused wires.
<suppressed ~2 debug messages>
6.6. Executing CHECK pass (checking for obvious problems).
checking module gpio_control_block..
found and reported 0 problems.
6.7. Executing OPT pass (performing simple optimizations).
6.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.
6.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.
6.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \gpio_control_block..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~4 debug messages>
6.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \gpio_control_block.
Performed a total of 0 changes.
6.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.
6.7.6. Executing OPT_DFF pass (perform DFF optimizations).
6.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>
6.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.
6.7.9. Rerunning OPT passes. (Maybe there is more to do..)
6.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \gpio_control_block..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~4 debug messages>
6.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \gpio_control_block.
Performed a total of 0 changes.
6.7.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.
6.7.13. Executing OPT_DFF pass (perform DFF optimizations).
6.7.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
6.7.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.
6.7.16. Finished OPT passes. (There is nothing left to do.)
6.8. Executing FSM pass (extract and optimize FSM).
6.8.1. Executing FSM_DETECT pass (finding FSMs in design).
6.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).
6.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).
6.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
6.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).
6.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
6.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
6.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
6.9. Executing OPT pass (performing simple optimizations).
6.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.
6.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.
6.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \gpio_control_block..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~4 debug messages>
6.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \gpio_control_block.
Performed a total of 0 changes.
6.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.
6.9.6. Executing OPT_DFF pass (perform DFF optimizations).
6.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
6.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.
6.9.9. Finished OPT passes. (There is nothing left to do.)
6.10. Executing WREDUCE pass (reducing word size of cells).
Removed top 1 bits (of 2) from port B of cell gpio_control_block.$eq$/project/openlane/gpio_control_block/../../verilog/rtl/gpio_control_block.v:205$18 ($eq).
6.11. Executing PEEPOPT pass (run peephole optimizers).
6.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
6.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module gpio_control_block:
created 0 $alu and 0 $macc cells.
6.14. Executing SHARE pass (SAT-based resource sharing).
6.15. Executing OPT pass (performing simple optimizations).
6.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.
6.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.
6.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \gpio_control_block..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~4 debug messages>
6.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \gpio_control_block.
Performed a total of 0 changes.
6.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.
6.15.6. Executing OPT_DFF pass (perform DFF optimizations).
6.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
6.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.
6.15.9. Finished OPT passes. (There is nothing left to do.)
6.16. Executing MEMORY pass.
6.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.
6.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
6.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
6.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
6.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
6.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).
6.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
6.18. Executing OPT pass (performing simple optimizations).
6.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.
<suppressed ~3 debug messages>
6.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.
6.18.3. Executing OPT_DFF pass (perform DFF optimizations).
6.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>
6.18.5. Finished fast OPT passes.
6.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
6.20. Executing OPT pass (performing simple optimizations).
6.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.
6.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.
6.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \gpio_control_block..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~3 debug messages>
6.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \gpio_control_block.
Performed a total of 0 changes.
6.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.
6.20.6. Executing OPT_SHARE pass.
6.20.7. Executing OPT_DFF pass (perform DFF optimizations).
6.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
6.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.
6.20.10. Finished OPT passes. (There is nothing left to do.)
6.21. Executing TECHMAP pass (map to technology primitives).
6.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
6.21.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $adff.
No more expansions possible.
<suppressed ~93 debug messages>
6.22. Executing OPT pass (performing simple optimizations).
6.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.
<suppressed ~3 debug messages>
6.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.
6.22.3. Executing OPT_DFF pass (perform DFF optimizations).
6.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
Removed 1 unused cells and 3 unused wires.
<suppressed ~2 debug messages>
6.22.5. Finished fast OPT passes.
6.23. Executing ABC pass (technology mapping using ABC).
6.23.1. Extracting gate netlist of module `\gpio_control_block' to `<abc-temp-dir>/input.blif'..
Extracted 15 gates and 28 wires to a netlist network with 12 inputs and 6 outputs.
6.23.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC:
ABC: + read_blif <abc-temp-dir>/input.blif
ABC: + read_library <abc-temp-dir>/stdcells.genlib
ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib".
ABC: + strash
ABC: + dretime
ABC: + map
ABC: + write_blif <abc-temp-dir>/output.blif
6.23.1.2. Re-integrating ABC results.
ABC RESULTS: AND cells: 2
ABC RESULTS: ANDNOT cells: 1
ABC RESULTS: MUX cells: 4
ABC RESULTS: NOR cells: 1
ABC RESULTS: NOT cells: 2
ABC RESULTS: ORNOT cells: 2
ABC RESULTS: internal signals: 10
ABC RESULTS: input signals: 12
ABC RESULTS: output signals: 6
Removing temp directory.
6.24. Executing OPT pass (performing simple optimizations).
6.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.
<suppressed ~2 debug messages>
6.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.
6.24.3. Executing OPT_DFF pass (perform DFF optimizations).
6.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
Removed 1 unused cells and 28 unused wires.
<suppressed ~3 debug messages>
6.24.5. Finished fast OPT passes.
6.25. Executing HIERARCHY pass (managing design hierarchy).
6.25.1. Analyzing design hierarchy..
Top module: \gpio_control_block
6.25.2. Analyzing design hierarchy..
Top module: \gpio_control_block
Removed 0 unused modules.
6.26. Printing statistics.
=== gpio_control_block ===
Number of wires: 43
Number of wire bits: 59
Number of public wires: 37
Number of public wire bits: 53
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 39
$_ANDNOT_ 1
$_AND_ 2
$_DFF_PP0_ 23
$_DFF_PP1_ 3
$_MUX_ 4
$_NOR_ 1
$_NOT_ 1
$_ORNOT_ 2
sky130_fd_sc_hd__conb_1 1
sky130_fd_sc_hd__einvp_8 1
6.27. Executing CHECK pass (checking for obvious problems).
checking module gpio_control_block..
found and reported 0 problems.
7. Executing SHARE pass (SAT-based resource sharing).
8. Executing OPT pass (performing simple optimizations).
8.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.
8.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.
8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \gpio_control_block..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \gpio_control_block.
Performed a total of 0 changes.
8.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\gpio_control_block'.
Removed a total of 0 cells.
8.6. Executing OPT_DFF pass (perform DFF optimizations).
8.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
8.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module gpio_control_block.
8.9. Finished OPT passes. (There is nothing left to do.)
9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
Removed 0 unused cells and 9 unused wires.
<suppressed ~9 debug messages>
10. Printing statistics.
=== gpio_control_block ===
Number of wires: 34
Number of wire bits: 48
Number of public wires: 28
Number of public wire bits: 42
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 39
$_ANDNOT_ 1
$_AND_ 2
$_DFF_PP0_ 23
$_DFF_PP1_ 3
$_MUX_ 4
$_NOR_ 1
$_NOT_ 1
$_ORNOT_ 2
sky130_fd_sc_hd__conb_1 1
sky130_fd_sc_hd__einvp_8 1
11. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
cell sky130_fd_sc_hd__dfxtp_4 (noninv, pins=3, area=23.77) is a direct match for cell type $_DFF_P_.
cell sky130_fd_sc_hd__dfrtp_4 (noninv, pins=4, area=28.78) is a direct match for cell type $_DFF_PN0_.
cell sky130_fd_sc_hd__dfstp_4 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFF_PN1_.
cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
final dff cell mappings:
unmapped dff cell: $_DFF_N_
\sky130_fd_sc_hd__dfxtp_4 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
unmapped dff cell: $_DFF_NN0_
unmapped dff cell: $_DFF_NN1_
unmapped dff cell: $_DFF_NP0_
unmapped dff cell: $_DFF_NP1_
\sky130_fd_sc_hd__dfrtp_4 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
\sky130_fd_sc_hd__dfstp_4 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
unmapped dff cell: $_DFF_PP0_
unmapped dff cell: $_DFF_PP1_
\sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
unmapped dff cell: $_DFFSR_NNP_
unmapped dff cell: $_DFFSR_NPN_
unmapped dff cell: $_DFFSR_NPP_
unmapped dff cell: $_DFFSR_PNN_
unmapped dff cell: $_DFFSR_PNP_
unmapped dff cell: $_DFFSR_PPN_
unmapped dff cell: $_DFFSR_PPP_
11.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\gpio_control_block':
mapped 23 $_DFF_PN0_ cells to \sky130_fd_sc_hd__dfrtp_4 cells.
mapped 3 $_DFF_PN1_ cells to \sky130_fd_sc_hd__dfstp_4 cells.
12. Printing statistics.
=== gpio_control_block ===
Number of wires: 60
Number of wire bits: 74
Number of public wires: 28
Number of public wire bits: 42
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 65
$_ANDNOT_ 1
$_AND_ 2
$_MUX_ 4
$_NOR_ 1
$_NOT_ 27
$_ORNOT_ 2
sky130_fd_sc_hd__conb_1 1
sky130_fd_sc_hd__dfrtp_4 23
sky130_fd_sc_hd__dfstp_4 3
sky130_fd_sc_hd__einvp_8 1
13. Executing ABC pass (technology mapping using ABC).
13.1. Extracting gate netlist of module `\gpio_control_block' to `/tmp/yosys-abc-cynOzn/input.blif'..
Extracted 37 gates and 49 wires to a netlist network with 12 inputs and 31 outputs.
13.1.1. Executing ABC.
Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-cynOzn/abc.script 2>&1
ABC: ABC command line: "source /tmp/yosys-abc-cynOzn/abc.script".
ABC:
ABC: + read_blif /tmp/yosys-abc-cynOzn/input.blif
ABC: + read_lib -w /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/trimmed.lib
ABC: Parsing finished successfully. Parsing time = 0.02 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/project/openlane/gpio_control_block/runs/gpio_control_block/tmp/trimmed.lib" has 43 cells (6 skipped: 6 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.03 sec
ABC: Memory = 1.82 MB. Time = 0.03 sec
ABC: + read_constr -v /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/synthesis/yosys.sdc
ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8".
ABC: Setting output load to be 17.650000.
ABC: + read_constr /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/synthesis/yosys.sdc
ABC: + fx
ABC: The network is unchanged by fast extract.
ABC: + mfs
ABC: + strash
ABC: + refactor
ABC: + balance
ABC: + rewrite
ABC: + refactor
ABC: + balance
ABC: + rewrite
ABC: + rewrite -z
ABC: + balance
ABC: + refactor -z
ABC: + rewrite -z
ABC: + balance
ABC: + retime -D -D 10000 -M 5
ABC: + scleanup
ABC: Error: The network is combinational.
ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000
ABC: + retime -D -D 10000
ABC: + buffer -N 5 -S 1000.0
ABC: + upsize -D 10000
ABC: Current delay (728.10 ps) does not exceed the target delay (10000.00 ps). Upsizing is not performed.
ABC: + dnsize -D 10000
ABC: + stime -p
ABC: WireLoad = "none" Gates = 43 ( 79.1 %) Cap = 13.1 ff ( 0.0 %) Area = 277.77 (100.0 %) Delay = 728.10 ps ( 9.3 %)
ABC: Path 0 -- 6 : 0 1 pi A = 0.00 Df = 6.1 -4.2 ps S = 17.8 ps Cin = 0.0 ff Cout = 4.6 ff Cmax = 0.0 ff G = 0
ABC: Path 1 -- 77 : 1 1 sky130_fd_sc_hd__inv_2 A = 3.75 Df = 24.9 -0.9 ps S = 19.0 ps Cin = 4.5 ff Cout = 2.5 ff Cmax = 331.4 ff G = 53
ABC: Path 2 -- 78 : 3 2 sky130_fd_sc_hd__and3_4 A = 11.26 Df = 207.5 -24.4 ps S = 64.9 ps Cin = 2.4 ff Cout = 11.8 ff Cmax = 532.8 ff G = 462
ABC: Path 3 -- 79 : 2 1 sky130_fd_sc_hd__or2_4 A = 8.76 Df = 403.6 -87.4 ps S = 46.2 ps Cin = 2.4 ff Cout = 4.5 ff Cmax = 514.5 ff G = 179
ABC: Path 4 -- 81 : 5 1 sky130_fd_sc_hd__a32o_4 A = 21.27 Df = 728.1 -193.3 ps S = 83.2 ps Cin = 4.3 ff Cout = 17.6 ff Cmax = 536.5 ff G = 407
ABC: Start-point = pi5 (\pad_gpio_dm [2]). End-point = po26 (\pad_gpio_out).
ABC: + print_stats -m
ABC: netlist : i/o = 12/ 31 lat = 0 nd = 43 edge = 59 area =277.61 delay = 4.00 lev = 4
ABC: + write_blif /tmp/yosys-abc-cynOzn/output.blif
13.1.2. Re-integrating ABC results.
ABC RESULTS: sky130_fd_sc_hd__a32o_4 cells: 2
ABC RESULTS: sky130_fd_sc_hd__and2_4 cells: 2
ABC RESULTS: sky130_fd_sc_hd__and3_4 cells: 1
ABC RESULTS: sky130_fd_sc_hd__buf_2 cells: 31
ABC RESULTS: sky130_fd_sc_hd__inv_2 cells: 3
ABC RESULTS: sky130_fd_sc_hd__nand2_4 cells: 2
ABC RESULTS: sky130_fd_sc_hd__or2_4 cells: 2
ABC RESULTS: internal signals: 6
ABC RESULTS: input signals: 12
ABC RESULTS: output signals: 31
Removing temp directory.
14. Executing SETUNDEF pass (replace undef values with defined constants).
15. Executing HILOMAP pass (mapping to constant drivers).
16. Executing SPLITNETS pass (splitting up multi-bit signals).
17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \gpio_control_block..
Removed 0 unused cells and 50 unused wires.
<suppressed ~3 debug messages>
18. Executing INSBUF pass (insert buffer cells for connected wires).
19. Executing CHECK pass (checking for obvious problems).
checking module gpio_control_block..
found and reported 0 problems.
20. Printing statistics.
=== gpio_control_block ===
Number of wires: 77
Number of wire bits: 79
Number of public wires: 38
Number of public wire bits: 40
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 71
sky130_fd_sc_hd__a32o_4 2
sky130_fd_sc_hd__and2_4 2
sky130_fd_sc_hd__and3_4 1
sky130_fd_sc_hd__buf_2 31
sky130_fd_sc_hd__conb_1 1
sky130_fd_sc_hd__dfrtp_4 23
sky130_fd_sc_hd__dfstp_4 3
sky130_fd_sc_hd__einvp_8 1
sky130_fd_sc_hd__inv_2 3
sky130_fd_sc_hd__nand2_4 2
sky130_fd_sc_hd__or2_4 2
Chip area for module '\gpio_control_block': 1056.012800
21. Executing Verilog backend.
Dumping module `\gpio_control_block'.
Warnings: 1 unique messages, 1 total
End of script. Logfile hash: 43ae35894e, CPU: user 0.83s system 0.02s, MEM: 44.12 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 28% 4x stat (0 sec), 28% 2x read_liberty (0 sec), ...