| OpenROAD 0.9.0 e582f2522b |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| Notice 0: Reading LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef |
| Notice 0: Created 13 technology layers |
| Notice 0: Created 25 technology vias |
| Notice 0: Created 437 library cells |
| Notice 0: Finished LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef |
| Notice 0: |
| Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/floorplan/gpio_control_block.floorplan.def |
| Notice 0: Design: gpio_control_block |
| Notice 0: Created 24 pins. |
| Notice 0: Created 163 components and 783 component-terminals. |
| Notice 0: Created 79 nets and 210 connections. |
| Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/floorplan/gpio_control_block.floorplan.def |
| [INFO] DBU = 1000 |
| [INFO] SiteSize = (460, 2720) |
| [INFO] CoreAreaLxLy = (5520, 10880) |
| [INFO] CoreAreaUxUy = (49680, 81600) |
| [INFO] NumInstances = 163 |
| [INFO] NumPlaceInstances = 71 |
| [INFO] NumFixedInstances = 92 |
| [INFO] NumDummyInstances = 0 |
| [INFO] NumNets = 79 |
| [INFO] NumPins = 234 |
| [INFO] DieAreaLxLy = (0, 0) |
| [INFO] DieAreaUxUy = (175000, 95000) |
| [INFO] CoreAreaLxLy = (5520, 10880) |
| [INFO] CoreAreaUxUy = (49680, 81600) |
| [INFO] CoreArea = 3122995200 |
| [INFO] NonPlaceInstsArea = 245235200 |
| [INFO] PlaceInstsArea = 1056012800 |
| [INFO] Util(%) = 36.695652 |
| [INFO] StdInstsArea = 1056012800 |
| [INFO] MacroInstsArea = 0 |
| [InitialPlace] Iter: 1 CG Error: 6.34609e-08 HPWL: 5988180 |
| [InitialPlace] Iter: 2 CG Error: 7.24026e-08 HPWL: 4198379 |
| [InitialPlace] Iter: 3 CG Error: 8.2169e-08 HPWL: 4192359 |
| [InitialPlace] Iter: 4 CG Error: 9.17372e-08 HPWL: 4192710 |
| [InitialPlace] Iter: 5 CG Error: 8.62562e-08 HPWL: 4190771 |
| [INFO] FillerInit: NumGCells = 77 |
| [INFO] FillerInit: NumGNets = 79 |
| [INFO] FillerInit: NumGPins = 234 |
| [INFO] TargetDensity = 0.400000 |
| [INFO] AveragePlaceInstArea = 14873419 |
| [INFO] IdealBinArea = 37183548 |
| [INFO] IdealBinCnt = 83 |
| [INFO] TotalBinArea = 3122995200 |
| [INFO] BinCnt = (64, 64) |
| [INFO] BinSize = (690, 1105) |
| [INFO] NumBins = 4096 |
| [NesterovSolve] Iter: 1 overflow: 0.921829 HPWL: 2537273 |
| [NesterovSolve] Iter: 10 overflow: 0.880087 HPWL: 2505154 |
| [NesterovSolve] Iter: 20 overflow: 0.881818 HPWL: 2502236 |
| [NesterovSolve] Iter: 30 overflow: 0.881345 HPWL: 2502512 |
| [NesterovSolve] Iter: 40 overflow: 0.881332 HPWL: 2502442 |
| [NesterovSolve] Iter: 50 overflow: 0.881407 HPWL: 2502543 |
| [NesterovSolve] Finished with Overflow: 0.881401 |
| Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found. |
| Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found. |
| create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD) |
| set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)] |
| set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)] |
| puts "\[INFO\]: Setting output delay to: $output_delay_value" |
| [INFO]: Setting output delay to: 2.0 |
| puts "\[INFO\]: Setting input delay to: $input_delay_value" |
| [INFO]: Setting input delay to: 2.0 |
| set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]] |
| #set rst_indx [lsearch [all_inputs] [get_port resetn]] |
| set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx] |
| #set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx] |
| set all_inputs_wo_clk_rst $all_inputs_wo_clk |
| # correct resetn |
| set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst |
| #set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn} |
| set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs] |
| # TODO set this as parameter |
| set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] |
| set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] |
| puts "\[INFO\]: Setting load to: $cap_load" |
| [INFO]: Setting load to: 0.01765 |
| set_load $cap_load [all_outputs] |
