openlane/gpio_control_block/runs/gpio_control_block/logs/lvs/write_powered_verilog.log

Notice 0: Reading LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/routing/gpio_control_block.def
Notice 0: Design: gpio_control_block
Notice 0:     Created 26 pins.
Notice 0:     Created 345 components and 1518 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 82 nets and 217 connections.
Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/routing/gpio_control_block.def
Top-level design name: gpio_control_block
Found port VPWR of type SIGNAL
Found port VGND of type SIGNAL
Power net:  VPWR
Ground net: VGND
Modified power connections of 345 cells (Remaining: 0 ).