| Notice 0: Reading LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged.lef |
| Notice 0: Created 13 technology layers |
| Notice 0: Created 25 technology vias |
| Notice 0: Created 437 library cells |
| Notice 0: Finished LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged.lef |
| Notice 0: |
| Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/verilog2def_openroad.def |
| Notice 0: Design: gpio_control_block |
| Notice 0: Created 24 pins. |
| Notice 0: Created 71 components and 495 component-terminals. |
| Notice 0: Created 79 nets and 210 connections. |
| Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/verilog2def_openroad.def |
| Top-level design name: gpio_control_block |
| Block boundaries: 0 0 175000 95000 |
| Writing /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/floorplan/ioPlacer.def |
