| OpenROAD 0.9.0 e582f2522b |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| Notice 0: Reading LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef |
| Notice 0: Created 13 technology layers |
| Notice 0: Created 25 technology vias |
| Notice 0: Created 437 library cells |
| Notice 0: Finished LEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/tmp/merged_unpadded.lef |
| Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found. |
| Notice 0: |
| Reading DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/placement/gpio_control_block.placement.def |
| Notice 0: Design: gpio_control_block |
| Notice 0: Created 24 pins. |
| Notice 0: Created 163 components and 783 component-terminals. |
| Notice 0: Created 79 nets and 210 connections. |
| Notice 0: Finished DEF file: /project/openlane/gpio_control_block/runs/gpio_control_block/results/placement/gpio_control_block.placement.def |
| [INFO]: Setting output delay to: 2.0 |
| [INFO]: Setting input delay to: 2.0 |
| [INFO]: Setting load to: 0.01765 |
| [INFO]: Configuring cts characterization... |
| [INFO]: Performing clock tree synthesis... |
| [INFO]: Looking for the following net(s): serial_clock |
| ***************** |
| * TritonCTS 2.0 * |
| ***************** |
| ***************************** |
| * Create characterization * |
| ***************************** |
| Number of created patterns = 50000. |
| Number of created patterns = 100000. |
| Number of created patterns = 150000. |
| Number of created patterns = 200000. |
| Number of created patterns = 250000. |
| Number of created patterns = 300000. |
| Number of created patterns = 313632. |
| Compiling LUT |
| Min. len Max. len Min. cap Max. cap Min. slew Max. slew |
| 2 8 1 39 1 199 |
| [WARNING] 6336 wires are pure wire and no slew degration. |
| TritonCTS forced slew degradation on these wires. |
| Num wire segments: 216048 |
| Num keys in characterization LUT: 1887 |
| Actual min input cap: 2 |
| ********************** |
| * Find clock roots * |
| ********************** |
| Running TritonCTS with user-specified clock roots: serial_clock |
| ************************ |
| * Populate TritonCTS * |
| ************************ |
| Initializing clock nets |
| Looking for clock nets in the design |
| Net "serial_clock" found |
| Initializing clock net for : "serial_clock" |
| Clock net "serial_clock" has 15 sinks |
| TritonCTS found 1 clock nets. |
| **************************** |
| * Check characterization * |
| **************************** |
| The chacterization used 4 buffer(s) types. All of them are in the loaded DB. |
| *********************** |
| * Build clock trees * |
| *********************** |
| Generating H-Tree topology for net serial_clock... |
| Tot. number of sinks: 15 |
| Number of static layers: 0 |
| Wire segment unit: 13000 dbu (13 um) |
| Original sink region: [(13160, 20340), (34305, 69300)] |
| Normalized sink region: [(1.01231, 1.56462), (2.63885, 5.33077)] |
| Width: 1.62654 |
| Height: 3.76615 |
| [WARNING] Creating fake entries in the LUT. |
| Level 1 |
| Direction: Vertical |
| # sinks per sub-region: 8 |
| Sub-region size: 1.62654 X 1.88308 |
| Segment length (rounded): 1 |
| Key: 216280 outSlew: 11 load: 1 length: 1 isBuffered: 1 |
| Stop criterion found. Max number of sinks is (15) |
| Building clock sub nets... |
| Number of sinks covered: 15 |
| Clock topology of net "serial_clock" done. |
| **************** |
| * Post CTS opt * |
| **************** |
| Avg. source sink dist: 14020.5 dbu. |
| Num outlier sinks: 0 |
| ******************** |
| * Write data to DB * |
| ******************** |
| Writing clock net "serial_clock" to DB |
| Created 3 clock buffers. |
| Minimum number of buffers in the clock path: 2. |
| Maximum number of buffers in the clock path: 2. |
| Created 3 clock nets. |
| Fanout distribution for the current clock = 6:1, 9:1. |
| Max level of the clock tree: 1. |
| ... End of TritonCTS execution. |
| [INFO]: Legalizing... |
| Warning: could not find power special net |
| Design Stats |
| -------------------------------- |
| total instances 166 |
| multi row instances 0 |
| fixed instances 92 |
| nets 82 |
| design area 3123.0 u^2 |
| fixed area 245.2 u^2 |
| movable area 1088.5 u^2 |
| utilization 38 % |
| utilization padded 39 % |
| rows 26 |
| row height 2.7 u |
| |
| Placement Analysis |
| -------------------------------- |
| total displacement 39.1 u |
| average displacement 0.2 u |
| max displacement 11.2 u |
| original HPWL 4310.0 u |
| legalized HPWL 4336.1 u |
| delta HPWL 1 % |
| |