Google Git
Sign in
foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-008 / refs/heads/main / . / verilog / rtl
tree: 8222265c75124e99f4b2261371f4fbc1c9cb5198 [path history] [tgz]
  1. hs32_user_proj/
  2. hs32cpu
  3. caravel.v
  4. caravel_clocking.v
  5. caravel_netlists.v
  6. chip_io.v
  7. clock_div.v
  8. convert_gpio_sigs.v
  9. counter_timer_high.v
  10. counter_timer_low.v
  11. defines.v
  12. DFFRAM.v
  13. DFFRAMBB.v
  14. digital_pll.v
  15. digital_pll_controller.v
  16. gpio_control_block.v
  17. gpio_wb.v
  18. housekeeping_spi.v
  19. la_wb.v
  20. manifest
  21. mem_wb.v
  22. mgmt_core.v
  23. mgmt_protect.v
  24. mgmt_protect_hv.v
  25. mgmt_soc.v
  26. mprj2_logic_high.v
  27. mprj_ctrl.v
  28. mprj_io.v
  29. mprj_logic_high.v
  30. pads.v
  31. picorv32.v
  32. README
  33. ring_osc2x13.v
  34. simple_por.v
  35. simple_spi_master.v
  36. simpleuart.v
  37. sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
  38. spimemio.v
  39. sram_1rw1r_32_256_8_sky130.v
  40. storage.v
  41. storage_bridge_wb.v
  42. sysctrl.v
  43. user_id_programming.v
  44. user_proj_example.v
  45. user_project_wrapper.v
  46. wb_intercon.v