tree: 11a8f868a5f0bddcdc1d63868af249857945fc27 [path history] [tgz]
  1. caravel/
  2. hs32_nocaravel/
  3. wb_utests/
  4. dummy_slave.v
  5. README.md
verilog/dv/README.md

DV Tests

Organized into two subdirectories:

  • caravel: contains tests for both the mangement SoC and an example user project.
  • wb_utests: contains unit tests for the wishbone components residing at the management SoC private bus