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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-008 / a46e36d7ad0aa874c152edf080eae78b693a4208
commita46e36d7ad0aa874c152edf080eae78b693a4208[log] [tgz]
authorJeff DiCorpo <jeffdi@efabless.com>Fri Feb 19 01:25:33 2021 -0800
committerJeff DiCorpo <jeffdi@efabless.com>Fri Feb 19 01:25:33 2021 -0800
treed1c6013f067a1da05c09d2d390e981a660d1f177
parentfa32cc580e490b65040172d4b87576d54c84d22c [diff]
final gds & drc results
6 files changed
tree: d1c6013f067a1da05c09d2d390e981a660d1f177
  1. def/
  2. gds/
  3. images/
  4. lef/
  5. macros/
  6. mag/
  7. maglef/
  8. ngspice/
  9. openlane/
  10. qflow/
  11. scripts/
  12. signoff/
  13. spi/
  14. utils/
  15. verilog/
  16. .gitignore
  17. .gitmodules
  18. info.yaml
  19. LICENSE
  20. Makefile
  21. Makefile.master
  22. manifest
  23. mpw-one-b.md
  24. README.md
README.md

HSC Latte HS32 Core

The HSC Latte HS32 Core is a 32-bits RISC CPU. The HS32 Core has 32-bits instructions and 16 32-bits registers.

Below is a list of HS32 Core Project Directories:

RepositoryDescriptionLicenseIssuesStarsContributors
caravel-hs32coreCore HarnessLicenseIssuesStarsContributors
hs32core-rtlRTL Circuit DesignLicenseIssuesStarsContributors
hs32coreMain Project RepositoryLicenseIssuesStarsContributors

Table of Contents

Overview

HS32 is a RISC-type CPU. (...)

Block Diagram Overview

CPU Overview

Execution Unit Block Diagram

Execution Unit

Project Structure

PathDescription
verilog/rtl/hs32cpuCPU Core Submodule
verilog/rtl/hs32_user_projUser project files and wrapper
verilog/rtl/hs32cpu/docsDetailed core documentation
verilog/dv/hs32_nocaravelNo-caravel testbenches
verilog/dv/caravel/hs32_socCaravel-integrated testbenches

General Documentation

Instructions

  • Immediate value is 16-bits
  • Rd, Rn and Rm specify the way each register is wired to the ALU. In this case, Rd represents the read/write source/destination, Rm and Rn represents the 2 operands fed into the ALU; note that Rn will always have a barrel shifter in front of it.
  • Naming a register with Rd Rn Rm is always 4 bits
  • [xxx] = Dereference pointer, address is stored in xxx
  • sh(Rn) shifts contents of Rn left or right by an 5-bits amount

Encoding

These are the different encodings that instructions come in. All instructions are 32 bit. The first 8 bits is opcode. Rd, Rm, Rn are always in the same position in the instruciton if present indicates unused spacer value of X bits

  • Field Sizes:
    • Rd : 4 bit register name
    • Rm : 4 bit register name
    • Rn : 4 bit register name
    • Shift: 5 bit shift amount applied to Rn
    • Imm16: 16 bit literal field

System Details

There are 16 (r0-r15) general-purpose registers plus 4 privileged registers. In supervisor mode, r12-15 is separate from user-mode r12-15. In all modes, r14 and r15 will be used as the link register and stack pointer respectively.

Legend:

  • IRQs -- Interrupt Requests
  • SP -- Stack Pointer
  • LR -- Link Register
  • MCR -- Machine Configuration Register
  • IVT -- Interrupt Vector Table

Operation

During a mode switch, the return address will be stored in the appropriate LR and the return stack pointer will be stored in the appropriate SP.

For instance, an interrupt call from User mode will prompt a switch to IRQ mode. The return address and stack pointer of the caller will be stored in IRQ LR (r14) and IRQ SP (r15) respectively.

CPU Planned Pinout

WIP

Devboard Block Diagram

Timing Waveforms

Various timing diagrams of the address and data buses

Read Cycle

Clock Cycles: 4 minimum

Timing Requirements:

  • The duration of the TW read clock (no data input) is determined by the tpd of whichever memory chip used.
  • TW can span multiple clock periods to allow for different memory timings. This will allow the CPU to be clocked at a higher speed than the memory chips.

In the implementation, OE# is the AND of 2 signals, one leading edge and one falling edge-driven signals.

Write Cycle

Clock Cycles: 4 minimum

Timing Requirements:

  • See the read cycle specifications

License

Apache 2.0 LICENSE

HS32 Core - A 32-bits RISC Processor

  Copyright (c) 2020 The HSC Core Authors

  Licensed under the Apache License, Version 2.0 (the "License");
  you may not use this file except in compliance with the License.
  You may obtain a copy of the License at

      https://www.apache.org/licenses/LICENSE-2.0

  Unless required by applicable law or agreed to in writing, software
  distributed under the License is distributed on an "AS IS" BASIS,
  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  See the License for the specific language governing permissions and
  limitations under the License.