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verilog
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dv
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caravel/
hs32_nocaravel/
wb_utests/
dummy_slave.v
README.md
verilog/dv/README.md
DV Tests
Organized into two subdirectories:
caravel: contains tests for both the mangement SoC and an example user project.
wb_utests: contains unit tests for the wishbone components residing at the management SoC private bus