Updated submodule
diff --git a/verilog/rtl/hs32cpu b/verilog/rtl/hs32cpu
index f7cac12..53cb12d 160000
--- a/verilog/rtl/hs32cpu
+++ b/verilog/rtl/hs32cpu
@@ -1 +1 @@
-Subproject commit f7cac12ae37605067d46d87a6c361c51ea5b993a
+Subproject commit 53cb12d24426cce72ffac6a8057f95df8a6108c5