commit	47be46d65f17d1d41cbc344a270abcf71fa1cdc2	[log] [tgz]
author	Kevin Dai <kevin@plesk.anthonian.dev>	Fri Dec 11 22:08:06 2020 -0500
committer	Kevin Dai <kevin@plesk.anthonian.dev>	Fri Dec 11 22:08:06 2020 -0500
tree	146bd516ad845532437b00c22b996fc3a5ebc19b
parent	4ed7ff7ade7db7e555ddc9859616b10efe22ac75 [diff]

tree: 146bd516ad845532437b00c22b996fc3a5ebc19b

README.md

HSC Latte HS32 Core

The HSC Latte HS32 Core is a 32-bits RISC CPU. The HS32 Core has 32-bits instructions and 16 32-bits registers.

Below is a list of HS32 Core Project Directories:

Repository	Description	License	Issues	Stars	Contributors
caravel-hs32core	Core Harness
hs32core-rtl	RTL Circuit Design
hs32core	Main Project Repository

Intro

Instructions

Immediate value is 16-bits
Rd, Rn and Rm specify the way each register is wired to the ALU. In this case, Rd represents the read/write source/destination, Rm and Rn represents the 2 operands fed into the ALU; note that Rn will always have a barrel shifter in front of it.
Naming a register with Rd Rn Rm is always 4 bits
[xxx] = Dereference pointer, address is stored in xxx
sh(Rn) shifts contents of Rn left or right by an 5-bits amount

Encoding

These are the different encodings that instructions come in. All instructions are 32 bit. The first 8 bits is opcode. Rd, Rm, Rn are always in the same position in the instruciton if present indicates unused spacer value of X bits

Field Sizes:
- Rd : 4 bit register name
- Rm : 4 bit register name
- Rn : 4 bit register name
- Shift: 5 bit shift amount applied to Rn
- Imm16: 16 bit literal field

System Details

There are 16 (r0-r15) general-purpose registers plus 4 privileged registers. In supervisor mode, r12-15 is separate from user-mode r12-15. In all modes, r14 and r15 will be used as the link register and stack pointer respectively.

Legend:

IRQs -- Interrupt Requests
SP -- Stack Pointer
LR -- Link Register
MCR -- Machine Configuration Register
IVT -- Interrupt Vector Table

Operation

During a mode switch, the return address will be stored in the appropriate LR and the return stack pointer will be stored in the appropriate SP.

For instance, an interrupt call from User mode will prompt a switch to IRQ mode. The return address and stack pointer of the caller will be stored in IRQ LR (r14) and IRQ SP (r15) respectively.

CPU

Planned Pinout

Pin #	Name	Description
0-15	IO0-15	Address/Data Parallel Bus: These lines contain the time-multiplexed address (T1, T2) and data (TW, T4) buses. During the T1 cycle, bits A0-A7 of the address bus is outputted. Bit A0 is the BLE# signal. It is LOW during T1 if only the low 8-bits is to be transferred during memory or I/O operations.
16	ALE0	Address Latch Enable (LOW): HIGH during T1 to signal for the latching of the low 8-bits of the address signal. It is LOW otherwise.
17	ALE1	Address Latch Enable (HIGH): HIGH during T2 to signal for the latching of the high 8-bits of the address signal. It is LOW otherwise.
18	WE#	Write Enable: Write strobe is LOW during TW to indicate that the processor is performing an I/O or memory write operation.
19	OE#	Output Enable: When LOW, indicates that the processor IO lines are ready to accept/output data. It is held HIGH during T1 and T2.
20	BHE#	Bus High Enable: When LOW, signals for the high 8-bits to be transferred during memory or I/O operations.
22	PIO	IO Mode: When HIGH, indicates that the current operation is an I/O, not memory, operation. This results in the omittance of cycle T2.
23, 24	RX, TX	9600 Baud UART Interface
25-...	GPIO0-...	General Purpose Input/Output

Overview

CPU Overview

Devboard Block Diagram

Timing Waveforms

Various timing diagrams of the address and data buses

Read Cycle

Clock Cycles: 4 minimum

Timing Requirements:

The duration of the TW read clock (no data input) is determined by the tpd of whichever memory chip used.
TW can span multiple clock periods to allow for different memory timings. This will allow the CPU to be clocked at a higher speed than the memory chips.

In the implementation, OE# is the AND of 2 signals, one leading edge and one falling edge-driven signals.

Write Cycle

Clock Cycles: 4 minimum

Timing Requirements:

See the read cycle specifications

Execution Unit

Docs

Directories

HS32 RTL -- verilog/rtl/hs32cpu

Documentation -- verilog/rtl/hs32cpu/docs

Testbenches -- verilog/rtl/hs32cpu/bench

CPU Modules -- verilog/rtl/hs32cpu/cpu

Frontend Modules -- verilog/rtl/hs32cpu/frontend

SOC Modules -- verilog/rtl/hs32cpu/soc

Third Party Modules -- verilog/rtl/hs32cpu/third_party

Programmer -- verilog/rtl/hs32cpu/programmer

Openlane -- verilog/rtl/hs32cpu/openlane

Skywater -- verilog/rtl/hs32cpu/skywater

Files

HS32 ISA -- verilog/rtl/hs32cpu/docs/isa_formal.txt

Top Level Module -- verilog/rtl/hs32cpu/top.v

HS32 Interrupts -- verilog/rtl/hs32cpu/docs/interrupts.md

HS32 MMIO -- verilog/rtl/hs32cpu/docs/mmio.md

Install

Usage

Contributing

Issues and pull requests are welcome! Please make sure to create them at the right repository :D

Security

We take any security risks seriously, if you have found or suspected a vulnerability or anything that might compromise our security, we would very much appreciate it if you can report it to us.

License

Apache 2.0 LICENSE

HS32 Core - A 32-bits RISC Processor

  Copyright (c) 2020 The HSC Core Authors

  Licensed under the Apache License, Version 2.0 (the "License");
  you may not use this file except in compliance with the License.
  You may obtain a copy of the License at

      https://www.apache.org/licenses/LICENSE-2.0

  Unless required by applicable law or agreed to in writing, software
  distributed under the License is distributed on an "AS IS" BASIS,
  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  See the License for the specific language governing permissions and
  limitations under the License.