Updated storage area
- Now has 2 blocks; one rw and one ro
diff --git a/verilog/dv/caravel/defs.h b/verilog/dv/caravel/defs.h
index 0aba014..2402f47 100644
--- a/verilog/dv/caravel/defs.h
+++ b/verilog/dv/caravel/defs.h
@@ -13,12 +13,9 @@
extern uint32_t flashio_worker_end;
// Storage area (MGMT: 0x0100_0000, User: 0x0200_0000)
-#define reg_mgmt_block0 (*(volatile uint32_t*)0x01000000)
-#define reg_mgmt_block1 (*(volatile uint32_t*)0x01100000)
-#define reg_user_block0 (*(volatile uint32_t*)0x02000000)
-#define reg_user_block1 (*(volatile uint32_t*)0x02100000)
-#define reg_user_block2 (*(volatile uint32_t*)0x02200000)
-#define reg_user_block3 (*(volatile uint32_t*)0x02300000)
+#define reg_rw_block0 (*(volatile uint32_t*)0x01000000)
+#define reg_rw_block1 (*(volatile uint32_t*)0x01100000)
+#define reg_ro_block0 (*(volatile uint32_t*)0x02000000)
// UART (0x2000_0000)
#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
diff --git a/verilog/dv/caravel/mgmt_soc/storage/storage.c b/verilog/dv/caravel/mgmt_soc/storage/storage.c
index 62a9428..b5f7408 100644
--- a/verilog/dv/caravel/mgmt_soc/storage/storage.c
+++ b/verilog/dv/caravel/mgmt_soc/storage/storage.c
@@ -40,12 +40,12 @@
// Test Management R/W block0
for (i=0; i<10; i++){
- ram_addr = ®_mgmt_block0 + i;
+ ram_addr = ®_rw_block0 + i;
*ram_addr = i*5000 + 10000;
}
for (i=0; i<10; i++){
- ram_addr = ®_mgmt_block0 + i;
+ ram_addr = ®_rw_block0 + i;
if ((i*5000+10000) != *ram_addr)
reg_mprj_datal = 0xAB400000;
}
@@ -55,12 +55,12 @@
// Test Management R/W block1
reg_mprj_datal = 0xA0200000;
for (i=0; i<10; i++){
- ram_addr = ®_mgmt_block1 + i;
+ ram_addr = ®_rw_block1 + i;
*ram_addr = i*5000 + 10000;
}
for (i=0; i<10; i++){
- ram_addr = ®_mgmt_block1 + i;
+ ram_addr = ®_rw_block1 + i;
if ((i*5000+10000) != *ram_addr)
reg_mprj_datal = 0xAB200000;
}
diff --git a/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v b/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
index 4d86f29..460f6d7 100644
--- a/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
+++ b/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
@@ -1,28 +1,23 @@
-
-`define MGMT_BLOCKS 2
-`define USER_BLOCKS 4
-`define MGMT_BASE_ADR 32'h 0100_0000
-`define USER_BASE_ADR 32'h 0200_0000
-
-`define MGMT_BLOCKS_ADR { \
- {24'h 10_0000}, \
- {24'h 00_0000} \
-}\
-
-`define USER_BLOCKS_ADR { \
- {24'h 00_0000}, \
- {24'h 10_0000}, \
- {24'h 20_0000}, \
- {24'h 30_0000} \
-}\
-
// `define DBG
+
+`define STORAGE_BASE_ADR 32'h0100_0000
+
+`include "defines.v"
`include "sram_1rw1r_32_256_8_sky130.v"
`include "storage.v"
`include "storage_bridge_wb.v"
module storage_tb;
+ localparam [(`RAM_BLOCKS*24)-1:0] STORAGE_RW_ADR = {
+ {24'h 10_0000},
+ {24'h 00_0000}
+ };
+
+ localparam [23:0] STORAGE_RO_ADR = {
+ {24'h 20_0000}
+ };
+
reg wb_clk_i;
reg wb_rst_i;
@@ -33,37 +28,22 @@
reg wb_cyc_i;
reg [1:0] wb_stb_i;
wire [1:0] wb_ack_o;
- wire [31:0] wb_mgmt_dat_o;
+ wire [31:0] wb_rw_dat_o;
- // MGMT_AREA RO WB Interface (USER_BLOCKS)
- wire [31:0] wb_user_dat_o;
+ // MGMT_AREA RO WB Interface
+ wire [31:0] wb_ro_dat_o;
- wire [`MGMT_BLOCKS-1:0] mgmt_ena;
- wire [(`MGMT_BLOCKS*4)-1:0] mgmt_wen_mask;
- wire [`MGMT_BLOCKS-1:0] mgmt_wen;
+ wire [`RAM_BLOCKS-1:0] mgmt_ena;
+ wire [(`RAM_BLOCKS*4)-1:0] mgmt_wen_mask;
+ wire [`RAM_BLOCKS-1:0] mgmt_wen;
wire [31:0] mgmt_wdata;
wire [7:0] mgmt_addr;
- wire [(`MGMT_BLOCKS*32)-1:0] mgmt_rdata;
- wire [`USER_BLOCKS-1:0] mgmt_user_ena;
- wire [7:0] mgmt_user_addr;
- wire [(`USER_BLOCKS*32)-1:0] mgmt_user_rdata;
-
- // USER_AREA R/W Interface (USER_BLOCKS)
- reg user_clk;
- reg [`USER_BLOCKS-1:0] user_ena;
- reg [`USER_BLOCKS-1:0] user_wen;
- reg [(`USER_BLOCKS*4)-1:0] user_wen_mask;
- reg [7:0] user_addr;
- reg [31:0] user_wdata;
- wire [(`USER_BLOCKS*32)-1:0] user_rdata;
-
- // USER_AREA RO Interface (MGMT_BLOCS)
- reg [`MGMT_BLOCKS-1:0] user_mgmt_ena;
- reg [7:0] user_mgmt_addr;
- wire [(`MGMT_BLOCKS*32)-1:0] user_mgmt_rdata;
+ wire [(`RAM_BLOCKS*32)-1:0] mgmt_rdata;
+ wire ro_ena;
+ wire [7:0] ro_addr;
+ wire [31:0] ro_rdata;
initial begin
- // MGMT Ports
wb_clk_i = 0;
wb_rst_i = 0;
wb_stb_i = 0;
@@ -72,21 +52,12 @@
wb_we_i = 0;
wb_dat_i = 0;
wb_adr_i = 0;
- // User Ports
- user_clk = 0;
- user_ena = {`USER_BLOCKS{1'b1}};
- user_wen = {`USER_BLOCKS{1'b1}};
- user_addr = 0;
- user_wdata = 0;
- user_mgmt_ena = {`MGMT_BLOCKS{1'b1}};
- user_mgmt_addr = 0;
end
always #1 wb_clk_i = ~wb_clk_i;
- always #1 user_clk = ~user_clk;
initial begin
- $dumpfile("storage_tb.vcd");
+ $dumpfile("storage.vcd");
$dumpvars(0, storage_tb);
repeat (100) begin
repeat (1000) @(posedge wb_clk_i);
@@ -98,11 +69,10 @@
end
reg [31:0] ref_data [255: 0];
- reg [24*(`MGMT_BLOCKS)-1:0] mgmt_blocks_adr = `MGMT_BLOCKS_ADR;
- reg [24*(`USER_BLOCKS)-1:0] user_blocks_adr = `USER_BLOCKS_ADR;
-
-
+ reg [(24*`RAM_BLOCKS)-1:0] storage_rw_adr = STORAGE_RW_ADR;
+ reg [23:0] storage_ro_adr = STORAGE_RO_ADR;
reg [31:0] block_adr;
+
integer i,j;
initial begin
@@ -113,59 +83,34 @@
#2;
// Test MGMT R/W port and user RO port
- for (i = 0; i< `MGMT_BLOCKS; i = i +1) begin
+ for (i = 0; i<`RAM_BLOCKS; i = i +1) begin
for ( j = 0; j < 100; j = j + 1) begin
if (i == 0) begin
ref_data[j] = $urandom_range(0, 2**30);
end
- block_adr = mgmt_blocks_adr[24*i+:24] + j | `MGMT_BASE_ADR;
- mgmt_write(block_adr, ref_data[j]);
+ block_adr = (storage_rw_adr[24*i+:24] + (j << 2)) | `STORAGE_BASE_ADR;
+ write(block_adr, ref_data[j]);
#2;
end
end
- for (i = 0; i< `MGMT_BLOCKS; i = i +1) begin
+ for (i = 0; i<`RAM_BLOCKS; i = i +1) begin
for ( j = 0; j < 100; j = j + 1) begin
- block_adr = mgmt_blocks_adr[24*i+:24] + j | `MGMT_BASE_ADR;
- mgmt_read(block_adr, 0);
- if (wb_mgmt_dat_o !== ref_data[j]) begin
+ block_adr = (storage_rw_adr[24*i+:24] + (j << 2)) | `STORAGE_BASE_ADR;
+ read(block_adr, 0);
+ if (wb_rw_dat_o !== ref_data[j]) begin
+ $display("Got %0h, Expected %0h from addr %0h: ",wb_rw_dat_o,ref_data[j], block_adr);
$display("Monitor: MGMT R/W Operation Failed");
$finish;
end
- user_mgmt_read(j,i);
- if (user_mgmt_rdata[32*i+:32] !== ref_data[j]) begin
- $display("Monitor: User RO Operation Failed");
- $finish;
- end
- #2;
- end
- end
-
- // Test user R/W port & MGMT RO port
- for (i = 0; i<`USER_BLOCKS; i = i +1) begin
- for ( j = 0; j < 100; j = j + 1) begin
if (i == 0) begin
- ref_data[j] = $urandom_range(0, 2**30);
- end
- user_write(j, ref_data[j], i);
- #2;
- end
- end
-
- for (i = 0; i< `USER_BLOCKS; i = i +1) begin
- for ( j = 0; j < 100; j = j + 1) begin
- user_read(j,i);
- if (user_rdata[32*i+:32] !== ref_data[j]) begin
- $display("Monitor: User R/W Operation Failed");
- $finish;
- end
-
- block_adr = user_blocks_adr[24*i+:24] + j | `USER_BASE_ADR;
- mgmt_read(block_adr,1);
- if(wb_user_dat_o !== ref_data[j])begin
- $display("Monitor: MGMT RO Operation Failed");
- $finish;
+ block_adr = (storage_ro_adr + (j << 2)) | `STORAGE_BASE_ADR;
+ read(block_adr, 1);
+ if (wb_ro_dat_o !== ref_data[j]) begin
+ $display("Monitor: MGMT RO Operation Failed");
+ $finish;
+ end
end
#2;
end
@@ -175,57 +120,7 @@
$finish;
end
- task user_write;
- input [32:0] addr;
- input [32:0] data;
- input integer block;
- begin
- @(posedge user_clk) begin
- user_ena[block] = 0;
- user_wen[block] = 0;
- user_wen_mask[(block*4)+:4] = 4'b1111;
- user_wdata = data;
- user_addr = addr[7:0];
- $display("Write Cycle Started.");
- end
- #4;
- user_ena[block] = 1;
- user_wen_mask[(block*4)+:4] = 4'b0000;
- user_wen[block] = 1;
- $display("Write Cycle Ended.");
- end
- endtask
-
- task user_read;
- input [32:0] addr;
- input integer block;
- begin
- @(posedge user_clk) begin
- user_ena[block] = 0;
- user_addr = addr[7:0];
- $display("Read Cycle Started.");
- end
- #8;
- user_ena[block] = 1;
- $display("Read Cycle Ended.");
- end
- endtask
-
- task user_mgmt_read;
- input [32:0] addr;
- input integer block;
- begin
- @(posedge user_clk) begin
- user_mgmt_ena[block] = 0;
- user_mgmt_addr = addr[7:0];
- $display("Read Cycle Started.");
- end
- #8;
- $display("Read Cycle Ended.");
- end
- endtask
-
- task mgmt_write;
+ task write;
input [32:0] addr;
input [32:0] data;
begin
@@ -247,33 +142,29 @@
end
endtask
- task mgmt_read;
+ task read;
input [32:0] addr;
- input integer block;
+ input integer interface;
begin
@(posedge wb_clk_i) begin
- wb_stb_i[block] = 1;
+ wb_stb_i[interface] = 1;
wb_cyc_i = 1;
wb_we_i = 0;
wb_adr_i = addr;
$display("Read Cycle Started.");
end
// Wait for an ACK
- wait(wb_ack_o[block] == 1);
- wait(wb_ack_o[block] == 0);
+ wait(wb_ack_o[interface] == 1);
+ wait(wb_ack_o[interface] == 0);
wb_cyc_i = 0;
- wb_stb_i[block] = 0;
+ wb_stb_i[interface] = 0;
$display("Read Cycle Ended.");
end
endtask
storage_bridge_wb #(
- .USER_BLOCKS(`USER_BLOCKS),
- .MGMT_BLOCKS(`MGMT_BLOCKS),
- .MGMT_BASE_ADR(`MGMT_BASE_ADR),
- .USER_BASE_ADR(`USER_BASE_ADR),
- .MGMT_BLOCKS_ADR(`MGMT_BLOCKS_ADR),
- .USER_BLOCKS_ADR(`USER_BLOCKS_ADR)
+ .RW_BLOCKS_ADR(STORAGE_RW_ADR),
+ .RO_BLOCKS_ADR(STORAGE_RO_ADR)
) wb_bridge (
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
@@ -285,10 +176,10 @@
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.wb_ack_o(wb_ack_o),
- .wb_mgmt_dat_o(wb_mgmt_dat_o),
+ .wb_rw_dat_o(wb_rw_dat_o),
- // MGMT_AREA RO WB Interface (USER_BLOCKS)
- .wb_user_dat_o(wb_user_dat_o),
+ // MGMT_AREA RO WB Interface
+ .wb_ro_dat_o(wb_ro_dat_o),
// MGMT Area native memory interface
.mgmt_ena(mgmt_ena),
@@ -297,18 +188,13 @@
.mgmt_addr(mgmt_addr),
.mgmt_wdata(mgmt_wdata),
.mgmt_rdata(mgmt_rdata),
-
- // MGMT_AREA RO Interface (USER_BLOCKS)
- .mgmt_user_ena(mgmt_user_ena),
- .mgmt_user_addr(mgmt_user_addr),
- .mgmt_user_rdata(mgmt_user_rdata)
+ // MGMT_AREA RO Interface
+ .mgmt_ena_ro(ro_ena),
+ .mgmt_addr_ro(ro_addr),
+ .mgmt_rdata_ro(ro_rdata)
);
-
- storage #(
- .MGMT_BLOCKS(`MGMT_BLOCKS),
- .USER_BLOCKS(`USER_BLOCKS)
- ) uut (
+ storage uut (
// Management R/W WB interface
.mgmt_clk(wb_clk_i),
.mgmt_ena(mgmt_ena),
@@ -318,22 +204,9 @@
.mgmt_wdata(mgmt_wdata),
.mgmt_rdata(mgmt_rdata),
// Management RO interface
- .mgmt_user_ena(mgmt_user_ena),
- .mgmt_user_addr(mgmt_user_addr),
- .mgmt_user_rdata(mgmt_user_rdata),
- // User R/W interface
- .user_clk(user_clk),
- .user_ena(user_ena),
- .user_wen(user_wen),
- .user_wen_mask(user_wen_mask),
- .user_addr(user_addr),
- .user_wdata(user_wdata),
- .user_rdata(user_rdata),
- // User RO interface
- .user_mgmt_ena(user_mgmt_ena),
- .user_mgmt_addr(user_mgmt_addr),
- .user_mgmt_rdata(user_mgmt_rdata)
+ .mgmt_ena_ro(ro_ena),
+ .mgmt_addr_ro(ro_addr),
+ .mgmt_rdata_ro(ro_rdata)
);
-
endmodule
\ No newline at end of file
