Included the project to simulate instead of user_proj_example.v
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index fa85ee2..ba66df9 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -83,7 +83,8 @@
/*------------------------------*/
/* Include user project here */
/*------------------------------*/
-`include "user_proj_example.v"
+//`include "user_proj_example.v"
+`include "ibtida-soc/Ibtida_top_dffram_cv.v"
// `ifdef USE_OPENRAM
// `include "sram_1rw1r_32_256_8_sky130.v"
