Added a simple power-on-reset circuit with schmitt trigger output, and
decoupled the reset pin from the porb/porb_h. The reset for the
housekeeping SPI remains connected to porb and not the reset pin, so
that the processor can be put in reset but the housekeeping SPI can
be accessed in that state. That prevents the user from bricking the
system by having a program override the housekeeping SPI and then get
into an erroneous state.
diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
new file mode 100644
index 0000000..4b92a55
--- /dev/null
+++ b/verilog/rtl/simple_por.v
@@ -0,0 +1,52 @@
+module simple_por(
+ input vdd3v3,
+ input vss,
+ output porb_h
+);
+
+ wire mid, porb_h;
+ reg inode;
+
+ // This is a behavioral model! Actual circuit is a resitor dumping
+ // current (slowly) from vdd3v3 onto a capacitor, and this fed into
+ // two schmitt triggers for strong hysteresis/glitch tolerance.
+
+ initial begin
+ inode <= 1'b0;
+ end
+
+ // Emulate current source on capacitor as a 500ns delay either up or
+ // down.
+
+ always @(posedge vdd3v3) begin
+ #500 inode <= 1'b1;
+ end
+ always @(negedge vdd3v3) begin
+ #500 inode <= 1'b0;
+ end
+
+ // Instantiate two shmitt trigger buffers in series
+
+ sky130_fd_sc_hvl__schmittbuf hystbuf1 (
+`ifdef LVS
+ .VPWR(vdd3v3),
+ .VGND(vss),
+ .VPB(vdd3v3),
+ .VNB(vss),
+`endif
+ .A(inode),
+ .X(mid)
+ );
+
+ sky130_fd_sc_hvl__schmittbuf hystbuf2 (
+`ifdef LVS
+ .VPWR(vdd3v3),
+ .VGND(vss),
+ .VPB(vdd3v3),
+ .VNB(vss),
+`endif
+ .A(mid),
+ .X(porb_h)
+ );
+
+endmodule
