Added a simple power-on-reset circuit with schmitt trigger output, and
decoupled the reset pin from the porb/porb_h. The reset for the
housekeeping SPI remains connected to porb and not the reset pin, so
that the processor can be put in reset but the housekeeping SPI can
be accessed in that state. That prevents the user from bricking the
system by having a program override the housekeeping SPI and then get
into an erroneous state.
diff --git a/verilog/dv/caravel/defs.h b/verilog/dv/caravel/defs.h
index 559151d..ac5dfdf 100644
--- a/verilog/dv/caravel/defs.h
+++ b/verilog/dv/caravel/defs.h
@@ -112,12 +112,12 @@
#define GPIO_MODE_MGMT_STD_INPUT_NOPULL 0x0403
#define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 0x0803
#define GPIO_MODE_MGMT_STD_INPUT_PULLUP 0x0c03
-#define GPIO_MODE_MGMT_STD_OUTPUT 0x1801
+#define GPIO_MODE_MGMT_STD_OUTPUT 0x1809
#define GPIO_MODE_USER_STD_INPUT_NOPULL 0x0402
#define GPIO_MODE_USER_STD_INPUT_PULLDOWN 0x0802
#define GPIO_MODE_USER_STD_INPUT_PULLUP 0x0c02
-#define GPIO_MODE_USER_STD_OUTPUT 0x1800
+#define GPIO_MODE_USER_STD_OUTPUT 0x1808
// --------------------------------------------------------
#endif
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio.c b/verilog/dv/caravel/mgmt_soc/gpio/gpio.c
index 9053551..d58c176 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/gpio.c
+++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio.c
@@ -91,7 +91,7 @@
reg_mprj_data = 0xab000000;
while (1){
- int x = reg_mprj_data & 0xff0000;
+ int x = (reg_mprj_data & 0xff0000) >> 16;
reg_mprj_data = (x+1) << 24;
}
}
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
index 56781da..615e4d1 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
@@ -64,7 +64,6 @@
wire flash_io1;
reg RSTB;
- reg CSB, SCK, SDI;
wire SDO;
// Transactor
@@ -100,9 +99,6 @@
end
initial begin
- CSB <= 1'b1;
- SCK <= 1'b0;
- SDI <= 1'b0;
RSTB <= 1'b0;
#1000;
@@ -139,7 +135,7 @@
wire [11:0] noconnect;
wire [2:0] spi_sigs;
- assign spi_sigs = 3'b010;
+ assign spi_sigs = 3'b010; // Set SCK, CSB, and SDI
caravel uut (
.vdd3v3 (VDD3V3),
@@ -148,7 +144,6 @@
.clock (clock),
.gpio (gpio),
.mprj_io ({checkbits, noconnect[11:1],
- // SCK, CSB, SDI, SDO, noconnect[0]}),
spi_sigs, SDO, noconnect[0]}),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart.hex b/verilog/dv/caravel/mgmt_soc/uart/uart.hex
deleted file mode 100755
index bb0c729..0000000
--- a/verilog/dv/caravel/mgmt_soc/uart/uart.hex
+++ /dev/null
@@ -1,36 +0,0 @@
-@00000000
-93 00 00 00 93 01 00 00 13 02 00 00 93 02 00 00
-13 03 00 00 93 03 00 00 13 04 00 00 93 04 00 00
-13 05 00 00 93 05 00 00 13 06 00 00 93 06 00 00
-13 07 00 00 93 07 00 00 13 08 00 00 93 08 00 00
-13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00
-13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00
-13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00
-13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 45 1B
-93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1
-11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 00 00
-63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 11 22
-01 A0 01 00 B7 02 00 28 13 03 00 12 23 90 62 00
-A3 81 02 00 05 C6 21 4F 93 73 F6 0F 93 DE 73 00
-23 80 D2 01 93 EE 0E 01 23 80 D2 01 86 03 93 F3
-F3 0F 7D 1F E3 14 0F FE 23 80 62 00 A1 C9 13 0F
-00 02 83 23 05 00 A1 4F 93 DE F3 01 23 80 D2 01
-93 EE 0E 01 23 80 D2 01 83 CE 02 00 93 FE 2E 00
-93 DE 1E 00 86 03 B3 E3 D3 01 7D 1F 63 17 0F 00
-23 20 75 00 11 05 83 23 05 00 FD 1F E3 96 0F FC
-FD 15 F1 F1 63 04 0F 00 23 20 75 00 13 03 00 08
-A3 81 62 00 82 80 01 00 00 00 01 11 06 CE 22 CC
-00 10 AA 87 A3 07 F4 FE 03 47 F4 FE A9 47 63 14
-F7 00 35 45 DD 37 B7 07 00 20 91 07 03 47 F4 FE
-98 C3 01 00 F2 40 62 44 05 61 82 80 01 11 06 CE
-22 CC 00 10 23 26 A4 FE 19 A8 83 27 C4 FE 13 87
-17 00 23 26 E4 FE 83 C7 07 00 3E 85 7D 37 83 27
-C4 FE 83 C7 07 00 F5 F3 01 00 F2 40 62 44 05 61
-82 80 41 11 06 C6 22 C4 00 08 B7 07 00 20 13 07
-10 27 98 C3 B7 07 00 21 23 A0 07 00 B7 07 00 21
-91 07 23 A0 07 00 B7 07 00 21 05 47 98 C3 B7 07
-00 10 13 85 47 20 59 3F B7 07 00 10 13 85 87 20
-71 37 B7 07 00 21 09 47 98 C3 01 00 B2 40 22 44
-41 01 82 80 0A 00 00 00 4D 6F 6E 69 74 6F 72 3A
-20 54 65 73 74 20 55 41 52 54 20 28 52 54 4C 29
-20 70 61 73 73 65 64 0A 0A 00 00 00
