commit	ec30b5f5faaa6db992f684109570e52be348d033	[log] [tgz]
author	Hadir Khan <hadirkhan10@gmail.com>	Mon Dec 07 14:55:18 2020 +0500
committer	Hadir Khan <hadirkhan10@gmail.com>	Mon Dec 07 14:55:18 2020 +0500
tree	fe4e4dff457a4e31ec7201f3e55d9120736dd283
parent	b7fdfb7b87af6617f7201c5cba28ff4a37e7726b [diff]
parent	04a09804e9ac4b7edc8b04225c3f7fc081541c60 [diff]

tree: fe4e4dff457a4e31ec7201f3e55d9120736dd283

README.md

ابتدا(Ibtida) SoC - Google SKY130 Shuttle

An Soc designed to be included inside the Caravel, a template SoC for Google SKY130 free shuttles.

ابتدا means the start of something. This is a minimal SoC built around a RISC-V based 5 stage pipelined core Buraq-Mini. Both the SoC and the core are made from scratch using CHISEL HDL. The CHISEL source code as well as the emitted verilog are provided in the relvant folders. It is still Work In Progress (WIP). The current SoC architecture is given below.

<<<<<<< HEAD

Design hierarchy

Chisel source code is available here:

chisel/
├── Buraq-Mini (core source)
│   │–– RV32i
│       └── src
│–– TileLink  (bus source)
│   └── src
└── src (SoC source)

The emitted verilog is present here:

verilog/
├── rtl
│   ├──ibtida-soc
│   │  └── Ibtida_top_dffram_cv.v

The synthesized netlist is present here:

verilog/
├── gl
│   └── Ibtida_top_dffram_cv.v

The hardened macros are placed here:

def/
└── Ibtida_top_dffram_cv.def.gz

lef/
└── Ibtida_top_dffram_cv.lef

gds/
└── Ibtida_top_dffram_cv.gds.gz

Contributors

Main contributors are:

Engr. Muhammad Hadir Khan (RTL design based on CHISEL) (Owner).
Sajjad Ahmed (RTL design based on CHISEL).
Engr. Aireen Amir Jalal (APR flow with OpenLANE RTL-GDSII).

Other contributors: 4. Dr. Roomi Naqvi (Supervisor). 5. Dr. Ali Ahmed (Supervisor). 6. Usman Zain