Minor RTL fixes, switching to wrapped GPIOV2
- use USER2_ABUTMENT_PINS for the second of the vssio and vddio pads
- do core-facing power-to-signal connections using the auto-router
- fix corner pad power connections and keep them for LVS purposes
- add a bunch of missing USE_POWER_PINS guards
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index b5460f5..0b23a50 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -17,6 +17,7 @@
module user_project_wrapper #(
parameter BITS = 32
)(
+`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
@@ -25,6 +26,7 @@
inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground
+`endif
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
@@ -63,6 +65,7 @@
/*--------------------------------------*/
user_proj_example mprj (
+ `ifdef USE_POWER_PINS
.vdda1(vdda1), // User area 1 3.3V power
.vdda2(vdda2), // User area 2 3.3V power
.vssa1(vssa1), // User area 1 analog ground
@@ -71,6 +74,7 @@
.vccd2(vccd2), // User area 2 1.8V power
.vssd1(vssd1), // User area 1 digital ground
.vssd2(vssd2), // User area 2 digital ground
+ `endif
// MGMT core clock and reset
