Various corrections to simplify the user project I/O wiring
connections into the management area. Corrected testbenches
for hkspi, mem, uart, perf, and gpio.
diff --git a/verilog/dv/caravel/defs.h b/verilog/dv/caravel/defs.h
index ac5dfdf..660b103 100644
--- a/verilog/dv/caravel/defs.h
+++ b/verilog/dv/caravel/defs.h
@@ -15,6 +15,7 @@
// UART (0x2000_0000)
#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
#define reg_uart_data (*(volatile uint32_t*)0x20000004)
+#define reg_uart_enable (*(volatile uint32_t*)0x20000008)
// GPIO (0x2100_0000)
#define reg_gpio_data (*(volatile uint32_t*)0x21000000)
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/Makefile b/verilog/dv/caravel/mgmt_soc/hkspi/Makefile
index 31a859c..b3930e2 100644
--- a/verilog/dv/caravel/mgmt_soc/hkspi/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/hkspi/Makefile
@@ -1,3 +1,4 @@
+# ---- Test patterns for project striVe ----
FIRMWARE_PATH = ../..
RTL_PATH = ../../../../rtl
IP_PATH = ../../../../ip
@@ -16,7 +17,7 @@
%.vvp: %_tb.v %.hex
iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
$< -o $@
-
+
%.vcd: %.vvp
vvp $<
@@ -24,7 +25,9 @@
${GCC_PATH}/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
%.hex: %.elf
- ${GCC_PATH}/riscv32-unknown-elf-objcopy -O verilog $< /dev/stdout | sed -e '1 s/@10000000/@00000000/; 2,65537 d;' > $@
+ ${GCC_PATH}/riscv32-unknown-elf-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
%.bin: %.elf
${GCC_PATH}/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c
index a415214..03cb7f5 100644
--- a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c
+++ b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c
@@ -19,20 +19,57 @@
void main()
{
- // Set clock to 64 kbaud
- reg_uart_clkdiv = 625;
+ // This program is just to keep the processor busy while the
+ // housekeeping SPI is being accessed, to show that the
+ // processor is interrupted only when the reset is applied
+ // through the SPI.
- // NOTE: Crystal is running in simulation at 5MHz
- // Internal clock is 8x crystal, or 40MHz
- // Divided by clkdiv is 64 kHz
- // So at this crystal rate, use clkdiv = 4167 for 9600 baud.
+ // Configure I/O: High 16 bits of user area used for a 16-bit
+ // word to write and be detected by the testbench verilog.
+ // Only serial Tx line is used in this testbench. It connects
+ // to mprj_io[6]. Since all lines of the chip are input or
+ // high impedence on startup, the I/O has to be configured
+ // for output
- // This should appear at the output, received by the testbench UART.
- print("\n");
- print(" ____ _ ____ ____\n");
- print(" | _ \\(_) ___ ___/ ___| ___ / ___|\n");
- print(" | |_) | |/ __/ _ \\___ \\ / _ \\| |\n");
- print(" | __/| | (_| (_) |__) | (_) | |___\n");
- print(" |_| |_|\\___\\___/____/ \\___/ \\____|\n");
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Start test
+ reg_mprj_data = 0xa0000000;
+
+ // Set clock to 64 kbaud and enable the UART
+ reg_uart_clkdiv = 625;
+ reg_uart_enable = 1;
+
+ // Test message
+ print("\n");
+ print(" ____ _ ____ ____\n");
+ print(" | _ \\(_) ___ ___/ ___| ___ / ___|\n");
+ print(" | |_) | |/ __/ _ \\___ \\ / _ \\| |\n");
+ print(" | __/| | (_| (_) |__) | (_) | |___\n");
+ print(" |_| |_|\\___\\___/____/ \\___/ \\____|\n");
+
+ reg_mprj_data = 0xab000000;
}
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
index 13677f7..d139182 100644
--- a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
@@ -12,7 +12,11 @@
reg clock;
reg SDI, CSB, SCK, RSTB;
- wire [1:0] gpio;
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [9:0] noconnect;
+ wire uart_tx;
+ wire uart_rx;
wire flash_csb;
wire flash_clk;
@@ -119,52 +123,53 @@
RSTB <= 1'b1;
#2000;
- // First do a normal read from the housekeeping SPI to
+ // First do a normal read from the housekeeping SPI to
// make sure the housekeeping SPI works.
- start_csb();
- write_byte(8'h40); // Read stream command
- write_byte(8'h03); // Address (register 3 = product ID)
+ start_csb();
+ write_byte(8'h40); // Read stream command
+ write_byte(8'h03); // Address (register 3 = product ID)
read_byte(tbdata);
end_csb();
#10;
- $display("Read data = 0x%02x (should be 0x05)", tbdata);
+ $display("Read data = 0x%02x (should be 0x10)", tbdata);
// Toggle external reset
- start_csb();
- write_byte(8'h80); // Write stream command
- write_byte(8'h07); // Address (register 7 = external reset)
- write_byte(8'h01); // Data = 0x01 (apply external reset)
- end_csb();
+ start_csb();
+ write_byte(8'h80); // Write stream command
+ write_byte(8'h07); // Address (register 7 = external reset)
+ write_byte(8'h01); // Data = 0x01 (apply external reset)
+ end_csb();
- start_csb();
- write_byte(8'h80); // Write stream command
- write_byte(8'h07); // Address (register 7 = external reset)
- write_byte(8'h00); // Data = 0x00 (release external reset)
- end_csb();
+ start_csb();
+ write_byte(8'h80); // Write stream command
+ write_byte(8'h07); // Address (register 7 = external reset)
+ write_byte(8'h00); // Data = 0x00 (release external reset)
+ end_csb();
- // Read all registers (0 to 8)
- start_csb();
- write_byte(8'h40); // Read stream command
- write_byte(8'h00); // Address (register 3 = product ID)
+ // Read all registers (0 to 18)
+ start_csb();
+ write_byte(8'h40); // Read stream command
+ write_byte(8'h00); // Address (register 3 = product ID)
read_byte(tbdata);
+
$display("Read register 0 = 0x%02x (should be 0x00)", tbdata);
if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
read_byte(tbdata);
$display("Read register 1 = 0x%02x (should be 0x04)", tbdata);
- if(tbdata !== 8'h14) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h04) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
read_byte(tbdata);
$display("Read register 2 = 0x%02x (should be 0x56)", tbdata);
if(tbdata !== 8'h56) begin $display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish; end
read_byte(tbdata);
- $display("Read register 3 = 0x%02x (should be 0x05)", tbdata);
- if(tbdata !== 8'h05) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ $display("Read register 3 = 0x%02x (should be 0x10)", tbdata);
+ if(tbdata !== 8'h10) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
read_byte(tbdata);
- $display("Read register 4 = 0x%02x (should be 0x07)", tbdata);
- if(tbdata !== 8'h07) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ $display("Read register 4 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
read_byte(tbdata);
- $display("Read register 5 = 0x%02x (should be 0x01)", tbdata);
- if(tbdata !== 8'h01) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ $display("Read register 5 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
read_byte(tbdata);
$display("Read register 6 = 0x%02x (should be 0x00)", tbdata);
if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
@@ -172,8 +177,38 @@
$display("Read register 7 = 0x%02x (should be 0x00)", tbdata);
if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
read_byte(tbdata);
- $display("Read register 8 = 0x%02x (should be 0x00)", tbdata);
+ $display("Read register 8 = 0x%02x (should be 0x01)", tbdata);
+ if(tbdata !== 8'h01) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ read_byte(tbdata);
+ $display("Read register 9 = 0x%02x (should be 0x01)", tbdata);
+ if(tbdata !== 8'h01) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ read_byte(tbdata);
+ $display("Read register 10 = 0x%02x (should be 0x00)", tbdata);
if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ read_byte(tbdata);
+ $display("Read register 11 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ read_byte(tbdata);
+ $display("Read register 12 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ read_byte(tbdata);
+ $display("Read register 13 = 0x%02x (should be 0xff)", tbdata);
+ if(tbdata !== 8'hff) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ read_byte(tbdata);
+ $display("Read register 14 = 0x%02x (should be 0xef)", tbdata);
+ if(tbdata !== 8'hef) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ read_byte(tbdata);
+ $display("Read register 15 = 0x%02x (should be 0xff)", tbdata);
+ if(tbdata !== 8'hff) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ read_byte(tbdata);
+ $display("Read register 16 = 0x%02x (should be 0x03)", tbdata);
+ if(tbdata !== 8'h03) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ read_byte(tbdata);
+ $display("Read register 17 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ read_byte(tbdata);
+ $display("Read register 18 = 0x%02x (should be 0x04)", tbdata);
+ if(tbdata !== 8'h04) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
end_csb();
@@ -191,26 +226,27 @@
assign VSS = 1'b0;
assign VDD1V8 = 1'b1;
+ wire hk_sck;
+ wire hk_csb;
+ wire hk_sdi;
+
+ assign hk_sck = SCK;
+ assign hk_csb = CSB;
+ assign hk_sdi = SDI;
+
caravel uut (
.vdd3v3 (VDD3V3),
.vdd1v8 (VDD1V8),
.vss (VSS),
.clock (clock),
- .SDI (SDI),
- .SDO (SDO),
- .CSB (CSB),
- .SCK (SCK),
- .ser_rx (1'b0),
- .ser_tx (tbuart_rx),
- .irq (1'b0),
.gpio (gpio),
+ .mprj_io ({checkbits, noconnect[9:1], uart_tx, uart_rx,
+ hk_sck, hk_csb, hk_sdi, SDO, noconnect[0]}),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
- .flash_io2(flash_io2),
- .flash_io3(flash_io3),
- .RSTB (RSTB)
+ .resetb (RSTB)
);
spiflash #(
@@ -220,12 +256,12 @@
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
- .io2(flash_io2),
- .io3(flash_io3)
+ .io2(), // not used
+ .io3() // not used
);
tbuart tbuart (
- .ser_rx(tbuart_rx)
+ .ser_rx(uart_tx)
);
endmodule
diff --git a/verilog/dv/caravel/mgmt_soc/mem/mem.c b/verilog/dv/caravel/mgmt_soc/mem/mem.c
index 31d0f75..8f4b542 100644
--- a/verilog/dv/caravel/mgmt_soc/mem/mem.c
+++ b/verilog/dv/caravel/mgmt_soc/mem/mem.c
@@ -12,40 +12,65 @@
void main()
{
- int i;
+ int i;
- /* All GPIO pins are configured to be output */
- reg_gpio_data = 0;
- reg_gpio_ena = 0x0000;
+ /* Upper 16 user area pins are configured to be GPIO output */
- // start test
- reg_gpio_data = 0xA040;
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
- // Test Word R/W
- for(i=0; i<10; i++)
- ints[i] = i*5000 + 10000;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // start test
+ reg_mprj_data = 0xA0400000;
+
+ // Test Word R/W
+ for (i=0; i<10; i++)
+ ints[i] = i*5000 + 10000;
- for(i=0; i<10; i++)
- if((i*5000+10000) != ints[i]) reg_gpio_data = 0xAB40;
- reg_gpio_data = 0xAB41;
-
- // Test Half Word R/W
- reg_gpio_data = 0xA020;
- for(i=0; i<10; i++)
- shorts[i] = i*500 + 100;
-
- for(i=0; i<10; i++)
- if((i*500+100) != shorts[i]) reg_gpio_data = 0xAB20;
- reg_gpio_data = 0xAB21;
+ for (i=0; i<10; i++)
+ if ((i*5000+10000) != ints[i])
+ reg_mprj_data = 0xAB400000;
- // Test byte R/W
- reg_gpio_data = 0xA010;
- for(i=0; i<10; i++)
- bytes[i] = i*5 + 10;
+ reg_mprj_data = 0xAB410000;
- for(i=0; i<10; i++)
- if((i*5+10) != bytes[i]) reg_gpio_data = 0xAB10;
- reg_gpio_data = 0xAB11;
+ // Test Half Word R/W
+ reg_mprj_data = 0xA0200000;
+ for (i=0; i<10; i++)
+ shorts[i] = i*500 + 100;
+
+ for(i=0; i<10; i++)
+ if((i*500+100) != shorts[i])
+ reg_mprj_data = 0xAB200000;
+ reg_mprj_data = 0xAB210000;
+
+ // Test byte R/W
+ reg_mprj_data = 0xA0100000;
+ for(i=0; i<10; i++)
+ bytes[i] = i*5 + 10;
+
+ for(i=0; i<10; i++)
+ if((i*5+10) != bytes[i])
+ reg_mprj_data = 0xAB100000;
+
+ reg_mprj_data = 0xAB110000;
}
diff --git a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
index 5248cd7..d815b9d 100644
--- a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
@@ -25,17 +25,15 @@
module mem_tb;
reg clock;
+ reg RSTB;
- reg SDI, CSB, SCK, RSTB;
-
- wire [1:0] gpio;
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [15:0] noconnect;
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
- wire flash_io2;
- wire flash_io3;
- wire SDO;
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
@@ -51,9 +49,9 @@
$dumpfile("mem.vcd");
$dumpvars(0, mem_tb);
- // Repeat cycles of 1000 XCLK edges as needed to complete testbench
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (100) begin
- repeat (1000) @(posedge XCLK);
+ repeat (1000) @(posedge clock);
//$display("+1000 cycles");
end
$display("%c[1;31m",27);
@@ -63,52 +61,47 @@
end
initial begin
- CSB <= 1'b1;
- SCK <= 1'b0;
- SDI <= 1'b0;
RSTB <= 1'b0;
-
#1000;
RSTB <= 1'b1; // Release reset
#2000;
- CSB <= 1'b0; // Apply CSB to start transmission
end
- always @(gpio) begin
- if(gpio == 16'hA040) begin
+ always @(checkbits) begin
+ if(checkbits == 16'hA040) begin
$display("Mem Test (word rw) started");
end
- else if(gpio == 16'hAB40) begin
+ else if(checkbits == 16'hAB40) begin
$display("%c[1;31m",27);
$display("Monitor: Test MEM (RTL) [word rw] failed");
$display("%c[0m",27);
$finish;
end
- else if(gpio == 16'hAB41) begin
+ else if(checkbits == 16'hAB41) begin
$display("Monitor: Test MEM (RTL) [word rw] passed");
end
- else if(gpio == 16'hA020) begin
+ else if(checkbits == 16'hA020) begin
$display("Mem Test (short rw) started");
end
- else if(gpio == 16'hAB20) begin
+ else if(checkbits == 16'hAB20) begin
$display("%c[1;31m",27);
$display("Monitor: Test MEM (RTL) [short rw] failed");
$display("%c[0m",27);
$finish;
end
- else if(gpio == 16'hAB21) begin
+ else if(checkbits == 16'hAB21) begin
$display("Monitor: Test MEM (RTL) [short rw] passed");
end
- else if(gpio == 16'hA010) begin
+ else if(checkbits == 16'hA010) begin
$display("Mem Test (byte rw) started");
end
- else if(gpio == 16'hAB10) begin
+ else if(checkbits == 16'hAB10) begin
$display("%c[1;31m",27);
$display("Monitor: Test MEM (RTL) [byte rw] failed");
$display("%c[0m",27);
$finish;
end
- else if(gpio == 16'hAB11) begin
+ else if(checkbits == 16'hAB11) begin
$display("Monitor: Test MEM (RTL) [byte rw] passed");
$finish;
end
@@ -128,22 +121,13 @@
.vdd1v8 (VDD1V8),
.vss (VSS),
.clock (clock),
- .xclk (XCLK),
- .SDI (SDI),
- .SDO (SDO),
- .CSB (CSB),
- .SCK (SCK),
- .ser_rx (1'b0),
- .ser_tx (),
- .irq (1'b0),
.gpio (gpio),
+ .mprj_io ({checkbits, noconnect}),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
- .flash_io2(flash_io2),
- .flash_io3(flash_io3),
- .RSTB (RSTB)
+ .resetb (RSTB)
);
spiflash #(
@@ -153,8 +137,8 @@
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
- .io2(flash_io2),
- .io3(flash_io3)
+ .io2(), // not used
+ .io3() // not used
);
endmodule
diff --git a/verilog/dv/caravel/mgmt_soc/perf/perf.c b/verilog/dv/caravel/mgmt_soc/perf/perf.c
index bd94f5d..b0edcb9 100644
--- a/verilog/dv/caravel/mgmt_soc/perf/perf.c
+++ b/verilog/dv/caravel/mgmt_soc/perf/perf.c
@@ -12,22 +12,43 @@
int main()
{
- int i;
+ int i;
int sum = 0;
- /* All GPIO pins are configured to be output */
- reg_gpio_data = 0;
- reg_gpio_ena = 0x0000;
+ /* Upper 16 user area pins are configured to be GPIO output */
- // start test
- reg_gpio_data = 0xA000;
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_data = 0;
+
+ // start test
+ reg_mprj_data = 0xA0000000;
- for(i=0; i<100; i++)
- sum+=(sum + i);
+ for (i=0; i<100; i++)
+ sum += (sum + i);
- reg_gpio_data = 0xAB00;
+ reg_mprj_data = 0xAB000000;
return sum;
-
}
diff --git a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
index 61a044d..985ca3f 100644
--- a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
@@ -23,19 +23,17 @@
`include "caravel.v"
`include "spiflash.v"
-module striVe_perf_tb;
+module perf_tb;
reg clock;
+ reg RSTB;
- reg SDI, CSB, SCK, RSTB;
-
- wire [1:0] gpio;
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [15:0] noconnect;
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
- wire flash_io2;
- wire flash_io3;
- wire SDO;
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
@@ -50,15 +48,15 @@
reg [31:0] kcycles;
initial begin
- $dumpfile("striVe_perf.vcd");
- $dumpvars(0, striVe_perf_tb);
+ $dumpfile("perf.vcd");
+ $dumpvars(0, perf_tb);
kcycles = 0;
- // Repeat cycles of 1000 XCLK edges as needed to complete testbench
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (150) begin
- repeat (1000) @(posedge XCLK);
+ repeat (1000) @(posedge clock);
//$display("+1000 cycles");
- kcycles<=kcycles+1;
+ kcycles <= kcycles + 1;
end
$display("%c[1;31m",27);
$display ("Monitor: Timeout, Test Performance (RTL) Failed");
@@ -67,24 +65,19 @@
end
initial begin
- CSB <= 1'b1;
- SCK <= 1'b0;
- SDI <= 1'b0;
RSTB <= 1'b0;
-
#1000;
RSTB <= 1'b1; // Release reset
#2000;
- CSB <= 1'b0; // Apply CSB to start transmission
end
- always @(gpio) begin
+ always @(checkbits) begin
//#1 $display("GPIO state = %X ", gpio);
- if(gpio == 16'hA000) begin
+ if(checkbits == 16'hA000) begin
kcycles = 0;
$display("Performance Test started");
end
- else if(gpio == 16'hAB00) begin
+ else if(checkbits == 16'hAB00) begin
//$display("Monitor: number of cycles/100 iterations: %d KCycles", kcycles);
$display("Monitor: Test Performance (RTL) passed [%0d KCycles]", kcycles);
$finish;
@@ -104,22 +97,13 @@
.vdd1v8 (VDD1V8),
.vss (VSS),
.clock (clock),
- .xclk (XCLK),
- .SDI (SDI),
- .SDO (SDO),
- .CSB (CSB),
- .SCK (SCK),
- .ser_rx (1'b0),
- .ser_tx ( ),
- .irq (1'b0 ),
.gpio (gpio),
+ .mprj_io ({checkbits, noconnect}),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
- .flash_io2(flash_io2),
- .flash_io3(flash_io3),
- .RSTB (RSTB)
+ .resetb (RSTB)
);
spiflash #(
@@ -129,8 +113,8 @@
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
- .io2(flash_io2),
- .io3(flash_io3)
+ .io2(), // not used
+ .io3() // not used
);
endmodule
diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart.c b/verilog/dv/caravel/mgmt_soc/uart/uart.c
index bd4b67d..a0b5cc3 100644
--- a/verilog/dv/caravel/mgmt_soc/uart/uart.c
+++ b/verilog/dv/caravel/mgmt_soc/uart/uart.c
@@ -5,23 +5,48 @@
void main()
{
- // Set clock to 64 kbaud
- reg_uart_clkdiv = 625;
+ // Configure I/O: High 16 bits of user area used for a 16-bit
+ // word to write and be detected by the testbench verilog.
+ // Only serial Tx line is used in this testbench. It connects
+ // to mprj_io[6]. Since all lines of the chip are input or
+ // high impedence on startup, the I/O has to be configured
+ // for output
- // NOTE: XCLK is running in simulation at 40MHz
- // Divided by clkdiv is 64 kHz
- // So at this crystal rate, use clkdiv = 4167 for 9600 baud.
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
- /* Both GPIO pins are configured to be output */
- reg_gpio_data = 0;
- reg_gpio_ena = 0x0000;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
- // start test
- reg_gpio_data = 0x0001;
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
- // This should appear at the output, received by the testbench UART.
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Set clock to 64 kbaud and enable the UART
+ reg_uart_clkdiv = 625;
+ reg_uart_enable = 1;
+
+ // Start test
+ reg_mprj_data = 0xa0000000;
+
+ // This should appear at the output, received by the testbench UART.
print("\n");
- print("Monitor: Test UART (RTL) passed\n\n");
- reg_gpio_data = 0x0002;
-}
+ // print("Monitor: Test UART (RTL) passed\n\n");
+ print("X\n\n");
+ reg_mprj_data = 0xab000000;
+}
diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
index 4f879fe..425ef1e 100644
--- a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
@@ -29,13 +29,17 @@
reg SDI, CSB, SCK, RSTB;
- wire [1:0] gpio;
+ wire gpio;
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire flash_io2;
wire flash_io3;
+ wire [15:0] checkbits;
+ wire [13:0] noconnect;
+ wire uart_tx;
+ wire uart_rx;
wire SDO;
always #12.5 clock <= (clock === 1'b0);
@@ -67,12 +71,12 @@
CSB <= 1'b0;
end
- always @(gpio) begin
- if(gpio == 16'hA000) begin
+ always @(checkbits) begin
+ if(checkbits == 16'hA000) begin
$display("UART Test started");
end
- else if(gpio == 16'hAB00) begin
- #1000;
+ else if(checkbits == 16'hAB00) begin
+ #20000; // Allow time for last transmission
$finish;
end
end
@@ -90,21 +94,14 @@
.vdd1v8 (VDD1V8),
.vss (VSS),
.clock (clock),
- .SDI (SDI),
- .SDO (SDO),
- .CSB (CSB),
- .SCK (SCK),
- .ser_rx (1'b0),
- .ser_tx (tbuart_rx),
- .irq (1'b0),
.gpio (gpio),
+ .mprj_io ({checkbits, noconnect[13:5],
+ uart_tx, uart_rx, noconnect[4:0]}),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
- .flash_io2(flash_io2),
- .flash_io3(flash_io3),
- .RSTB (RSTB)
+ .resetb (RSTB)
);
spiflash #(
@@ -114,13 +111,13 @@
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
- .io2(flash_io2),
- .io3(flash_io3)
+ .io2(), // not used
+ .io3() // not used
);
// Testbench UART
tbuart tbuart (
- .ser_rx(tbuart_rx)
+ .ser_rx(uart_tx)
);
endmodule
