Merge branch 'master' of https://github.com/hadirkhan10/ibtida-soc
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@@ -1,28 +1,59 @@
-# ابتدا(Ibtida) SoC
+# ابتدا(Ibtida) SoC - Google SKY130 Shuttle
+An Soc designed to be included inside the Caravel, a template SoC for Google SKY130 free shuttles.
ابتدا means the start of something. This is a minimal SoC built around a RISC-V based 5 stage pipelined core Buraq-Mini. Both the SoC and the core are made from scratch using CHISEL HDL. The CHISEL source code as well as the emitted verilog are provided in the relvant folders. It is still Work In Progress (WIP). The current SoC architecture is given below.
<p align=”center”>
-<img src="/doc/IbtidaSoC.png" >
+<img src="/doc/ibtida-soc.png" >
</p>
+## Design hierarchy
+Chisel source code is available here:
+```
+chisel/
+├── Buraq-Mini (core source)
+│ │–– RV32i
+│ └── src
+│–– TileLink (bus source)
+│ └── src
+└── src (SoC source)
+```
+The emitted verilog is present here:
+```
+verilog/
+├── rtl
+│ ├──ibtida-soc
+│ │ └── Ibtida_top_dffram_cv.v
+```
+The synthesized netlist is present here:
+```
+verilog/
+├── gl
+│ └── Ibtida_top_dffram_cv.v
+```
+The hardened macros are placed here:
+```
+def/
+└── Ibtida_top_dffram_cv.def.gz
+```
+```
+lef/
+└── Ibtida_top_dffram_cv.lef
+```
+```
+gds/
+└── Ibtida_top_dffram_cv.gds.gz
+```
## Contributors
Main contributors are:
-1. Engr. Muhammad Hadir Khan (RTL design based on CHISEL)(Owner).
+1. Engr. Muhammad Hadir Khan (RTL design based on CHISEL) (__Owner__).
2. Sajjad Ahmed (RTL design based on CHISEL).
-3. Engr. Aireen Aamir Jalal (APR flow with OpenLANE RTL-GDSII).
-
+3. Engr. Aireen Amir Jalal (APR flow with OpenLANE RTL-GDSII).
Other contributors:
-1. Dr. Ali Ahmed (Supervisor).
-2. Dr. Roomi Naqvi (Supervisor).
-3. Engr. Farhan Ahmed Karim (Supervisor).
-4. Engr. Asad Hussain Jaffri (Supervisor).
-5. Zain Rizwan Khan
-6. Hamza Shabbir
-7. Uzair Khan
-8. Wajeh
-9. Usman Zain
-10. Zeeshan
-11. Waleed
+
+4. Dr. Roomi Naqvi (Supervisor).
+5. Dr. Ali Ahmed (Supervisor).
+6. Usman Zain
+
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