commit b78e1c1b303373a41e7a4901008735070424a88e
author Tim Edwards <tim@opencircuitdesign.com> Fri Oct 09 11:51:48 2020 -0400
committer Tim Edwards <tim@opencircuitdesign.com> Fri Oct 09 11:51:48 2020 -0400
tree 221f8d224b6101805fb9297181e8d0c9e8ef09ab
parent 0c0324003d728113a2379c191f41f9984a19e11b

Added management flash SPI pass-through mode testbench and debugged it.

verilog/rtl/spimemio.v

diff --git a/verilog/rtl/spimemio.v b/verilog/rtl/spimemio.v
index 2d0b6fe..074fff7 100644
--- a/verilog/rtl/spimemio.v
+++ b/verilog/rtl/spimemio.v
@@ -318,7 +318,7 @@
     assign flash_clk_ieb = 1'b1;	/* Always disabled */
 
     assign flash_io0_ieb = (pass_thru | ~resetn) ? 1'b1 : (config_en ? xfer_io0_oe : config_oe[0]);
-    assign flash_io1_ieb = (pass_thru | ~resetn) ? 1'b1 : (config_en ? xfer_io1_oe : config_oe[1]);
+    assign flash_io1_ieb = pass_thru ? 1'b0 : ~resetn ? 1'b1 : (config_en ? xfer_io1_oe : config_oe[1]);
     assign flash_io2_ieb = (pass_thru | ~resetn) ? 1'b1 : (config_en ? xfer_io2_oe : config_oe[2]);
     assign flash_io3_ieb = (pass_thru | ~resetn) ? 1'b1 : (config_en ? xfer_io3_oe : config_oe[3]);