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<img src="/doc/ibtida-soc.png" >
</p>
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## Design hierarchy
Chisel source code is available here:
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gds/
└── Ibtida_top_dffram_cv.gds.gz
```
+
+## Todo
+- [ ] Change the repo name to integrate "caravel_".
+- [ ] Update the project with the caravel mpw-one-a branch.
+- [ ] Update the openlane with the mpw-one-a branch.
+- [ ] Verify the synthesized netlist.
+- [ ] Harden the design macro with 0 drc/lvs violations.
+- [ ] Harden the user project wrapper with 0 drc/lvs violations.
+- [ ] On-board the user project to Caravel.
+- [ ] Pass all the pre-checks.
+- [ ] Update the request to "Submitter Confirmed".
+
## Contributors
Main contributors are:
1. Engr. Muhammad Hadir Khan (RTL design based on CHISEL) (__Owner__).
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3. Engr. Aireen Amir Jalal (APR flow with OpenLANE RTL-GDSII).
Other contributors:
+
4. Dr. Roomi Naqvi (Supervisor).
5. Dr. Ali Ahmed (Supervisor).
-6. Usman Zain
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+6. Usman Zain