| commit | 8923d7a2ef82946e63b3dbdfdf51d9ebb3e34028 | [log] [tgz] |
|---|---|---|
| author | hadirkhan10 <hadirkhan10@gmail.com> | Thu Dec 03 19:41:30 2020 +0000 |
| committer | hadirkhan10 <hadirkhan10@gmail.com> | Thu Dec 03 19:41:30 2020 +0000 |
| tree | 03bebab5ce63c60951c15b850b5ee854e43fd631 | |
| parent | f78084f15106f678ee394677faf3ccddd392be5b [diff] |
added the design to run through the openlane flow
ابتدا means the start of something. This is a minimal SoC built around a RISC-V based 5 stage pipelined core Buraq-Mini. Both the SoC and the core are made from scratch using CHISEL HDL. The CHISEL source code as well as the emitted verilog are provided in the relvant folders. It is still Work In Progress (WIP). The current SoC architecture is given below.
Main contributors are:
Other contributors: