Modified code to let SPI master control the housekeeping SPI through
a configuration bit setting in the SPI master. Revised the "sysctrl"
testbench to work with the SPI master controlling the housekeeping
SPI.
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index e5375ff..5f1050d 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -122,6 +122,9 @@
input pass_thru_mgmt_sdi,
output pass_thru_mgmt_sdo,
+ // SPI master->slave direct link
+ output hk_connect,
+
// WB MI A (Mega project)
input mprj_ack_i,
input [31:0] mprj_dat_i,
@@ -481,6 +484,7 @@
.wb_ack_o(spi_master_ack_o),
.wb_dat_o(spi_master_dat_o),
+ .hk_connect(hk_connect),
.csb(mgmt_out_pre[3]),
.sck(mgmt_out_pre[4]),
.sdi(mgmt_in_data[1]),
