Corrected the mess caused by introducing default_nettype none into the design
verification netlists. Also cleaned up the broken power-on-reset signaling,
and added connections from the user space to the I/O pad direct-to-pad analog
signal pins.
diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
index f6bda39..6307e79 100644
--- a/verilog/rtl/simple_por.v
+++ b/verilog/rtl/simple_por.v
@@ -69,5 +69,6 @@
// since this is behavioral anyway, but this should be
// replaced by a proper inverter
- assign por_l = porb_l;
+ assign por_l = ~porb_l;
endmodule
+`default_nettype wire
